Chapter 6: Engineering Outlook

Chapter 6: Outlook — From Current State to Early Prototypes

The preceding five chapters have systematically constructed a complete knowledge framework for understanding quantum computing: from linear algebra and complex numbers (Chapter 1), quantum mechanics principles (Chapter 2), qubits and quantum gates (Chapter 3), to stabilizer formalism, quantum error correction and magic state distillation (Chapter 4), and finally to the circuit implementation of the quantum Fourier transform, quantum phase estimation, noise models, and variational quantum algorithms (Chapter 5). These chapters present the theoretical foundations of quantum computing, recent algorithmic practices, and the core mechanisms of fault-tolerant quantum computing.

However, as of 2025, no quantum computing platform in the world can run a fault-tolerant quantum algorithm with practical application value. This chapter takes an engineering perspective to analyze the seven key engineering milestones that must be crossed to go from today’s demonstrations to early prototypes. This is not a manifesto of technological optimism, but a checklist of engineering obstacles — each milestone corresponds to specific quantitative metrics, physical limitations, and timeline uncertainties. Understanding these obstacles is a prerequisite for assessing when quantum computing can move from laboratory demonstrations to practical engineering.

6.1 Current State of the Art

Superconducting Route: Willow’s Breakthrough and Limitations

The Willow processor released by Google Quantum AI at the end of 2024 represented a milestone advance in the superconducting quantum computing route. Willow has 105 physical qubits and uses the Surface Code for quantum error correction storage demonstrations. Its core achievements include:

Error correction below threshold: Willow demonstrated for the first time in a superconducting system that the logical error rate of the surface code decreases exponentially with increasing code distance $d$ , proving the effectiveness of the error correction mechanism.
Logical error rate at distance $d=7$ : On the $d=7$ surface code, the logical error rate reached approximately $8 \times 10^{-6}$ , corresponding to an equivalent single-qubit error rate below the $10^{-3}$ threshold.
Real-time decoding: Willow integrated an FPGA-based real-time decoder capable of completing syndrome data processing and error correction feedback within the qubit coherence time.

However, Willow’s achievements are limited to storage error correction of quantum information. It did not demonstrate fault-tolerant logical gate operations, let alone the logical $T$ gate required for universal quantum computing. A key engineering detail is that Willow’s 105 qubits operate on a “carefully selected optimal subset” — meaning that on larger chips, fabrication non-uniformity will become a critical bottleneck.

Ion Trap Route: Quantinuum H2’s Logical Gate Demonstration

Quantinuum’s H2 processor (based on Honeywell’s ion trap technology) demonstrated another milestone in early 2025:

Complete set of fault-tolerant logical Clifford gates: H2 demonstrated the execution of the full Clifford gate set (Hadamard, Phase, CNOT) on logical qubits, with logical gate error rates below the logical error rate after storage error correction.
Logical magic state distillation: H2 further demonstrated magic state distillation at the logical level, preparing high-fidelity $|T\rangle$ states for subsequent logical $T$ gates.

Quantinuum H2 uses 56 ytterbium ions ( $^{171}\text{Yb}^+$ ) trapped in the same Paul trap, with quantum gates mediated by phonons. This platform significantly outperforms the superconducting route in gate fidelity (single-qubit > 99.9%, two-qubit ~99.5%) and coherence time ( $T_2 \sim 1\text{--}10\,\text{s}$ ). However, 56 ions is close to the upper limit that a single trap can support — increased phonon spectral density leads to crosstalk and reduced gate speed.

Early Progress on Other Platforms

Neutral Atom Route: Represented by QuEra, Pasqal, and Atom Computing, neutral atom platforms lead in qubit count (Atom Computing has achieved 1000+ atom arrays), but two-qubit gate fidelity still lags behind superconducting and ion trap platforms (~99.5%, compared to superconducting’s 99.9%+). The advantages of neutral atoms are their natural all-to-all connectivity and reconfigurable geometry, but atom loss and rearrangement remain unresolved engineering problems.

Photonic Route: Represented by PsiQuantum, photonic quantum computing uses photons as flying qubits, naturally suited for quantum communication and certain specific algorithms. PsiQuantum’s goal is to manufacture million-photon qubits through wafer-scale integration, but it is still in an early stage with immature logical gate demonstrations.

Silicon Spin Route: Represented by Intel and research groups at Delft, silicon spin qubits have the strongest CMOS process compatibility, but are currently the smallest in scale (~6—10 qubits), with immense challenges in quantum dot fabrication uniformity. Their advantage lies in potential scalability and synergy with the existing semiconductor ecosystem.

The Common Gap: Not a Computer

The common characteristic of all the above platforms is: they are demonstration devices for physical phenomena, not programmable general-purpose computers. Willow can store quantum information and correct errors, but cannot execute general algorithms; Quantinuum H2 can execute logical Clifford gates, but has not yet completed a fault-tolerant demonstration of the logical $T$ gate; neutral atom platforms have the most qubits, but their gate fidelity has not yet reached the fault-tolerant threshold; silicon spin platforms are theoretically the most scalable, but are currently the smallest.

Defined from an engineering perspective, an early prototype needs to satisfy the following minimum conditions:

1000—2000 high-quality physical qubits (assuming $d=15\text{--}25$ surface code + magic state distillation overhead)
Complete set of fault-tolerant logical gates (Clifford + $T$ gate)
Real-time, low-latency decoding system
Stable cryogenic/control environment supporting continuous operation for weeks
Automated calibration and error handling

The following six sections will analyze, one by one, the engineering obstacles from the current state to meeting the above conditions.

6.2 Qubit Scale-Up: From $10^2$ to $10^{3\text{--}4}$

Expanding from roughly 100 physical qubits to 1000—10000 is an engineering challenge spanning orders of magnitude. The bottlenecks differ across physical platforms, but all universally involve the fundamental contradiction among fabrication precision, control density, and crosstalk suppression.

Superconducting Route: The Triple Dilemma of Fabrication, Wiring, and Crosstalk

The superconducting qubit (Transmon) is the most technologically mature route，but its scaling faces three interconnected engineering problems。

Chip Yield and Fabrication Uniformity. Willow’s 105 qubits are not all usable — actual operation runs on a carefully selected optimal subset. When the qubit count increases to 1000+, the “subset selection” strategy will no longer be feasible: every physical qubit must operate reliably, otherwise the logical distance of the error-correcting code will be “punctured” by fabrication defects.

Specifically, the key parameters of each Josephson Junction — the charging energy $E_C$ and the Josephson energy $E_J$ — must maintain <1% variation across the full wafer. The $E_J/E_C$ ratio determines the qubit frequency, and frequency non-uniformity directly leads to:

Control pulses cannot be reused; each qubit requires independent calibration
Frequency crowding leads to uncontrollable $ZZ$ crosstalk
Readout resonator frequency overlap, reducing readout fidelity

Current fabrication yield for superconducting qubits is about 80—90% (measured by single-qubit operability), but a 1000-qubit system requires 99.9%+ yield — a precision level that took the semiconductor industry decades to achieve, and the superconducting qubit fabrication process (aluminum/niobium thin-film evaporation, electron-beam lithography, bilayer resist processes) is far more fragile than mature CMOS processes.

Thermodynamic Limit of Wiring Density. Each superconducting qubit requires at least 2—3 microwave control lines (XY control, Z control) and 1 readout resonator coupling line. 1000 qubits means 2000—3000 coaxial cables passing from room temperature through the various cold stages of a dilution refrigerator, ultimately reaching the 10 mK sample stage.

The thermal load per coaxial cable is 10—100 $\,\mu\text{W}$ (depending on material, diameter, and length). The total thermal load from 3000 cables can reach 30—300 $\,\text{mW}$ , while commercial dilution refrigerators have a cooling power of only 10—100 $\,\mu\text{W}$ at the 10 mK stage — a 3-orders-of-magnitude gap in thermal load. This means the current wiring scheme cannot linearly scale to 1000 qubits.

Candidate solutions include:

3D Integration: Integrate control electronics at the cryogenic stage (1K or lower), reducing the number of signal lines entering the 10 mK stage
On-Chip Multiplexing: Use frequency or time multiplexing to reduce physical connections
High-Temperature Superconducting Interconnects: Use high-temperature superconducting materials (such as YBCO) to reduce transmission heat load, but process compatibility between HTS and low-temperature superconducting qubits remains an unsolved problem

Exponential Degradation of Crosstalk Suppression. Superconducting qubits implement two-qubit gates (such as iSWAP or CZ gates) through capacitive coupling. When the qubit pitch is reduced to increase areal density, residual $ZZ$ coupling (unintended $Z \otimes Z$ interaction) increases exponentially. $ZZ$ coupling causes:

Single-qubit phase drift, requiring dynamical decoupling compensation
Two-qubit gate fidelity degradation, because unintended terms are mixed into the target Hamiltonian
Incoherent excitation of low-frequency qubits by high-frequency qubits (Spectator Qubit Errors)

Current $ZZ$ coupling suppression is achieved through tunable couplers, which can suppress $ZZ/2\pi$ to below <100 $\,\text{kHz}$ . However, in a 1000+ qubit 2D grid, long-range coupling (through substrate modes or control line crosstalk) will become a new limiting factor.

Ion Trap Route: Single-Trap Limits and Modular Interconnection

The scalability bottleneck of the ion trap route is fundamentally different from that of superconducting.

Phonon Mode Limitation in a Single Trap. The 56 ions in Quantinuum H2 share the phonon modes of the harmonic potential in the same Paul trap. Quantum gates achieve effective coupling between ions by driving specific phonon modes with lasers. As the number of ions increases:

Phonon spectral density increases, reducing the frequency spacing $\Delta\omega$ between adjacent modes
The frequency precision $\delta\omega \ll \Delta\omega$ required to address specific modes with lasers becomes difficult to satisfy
Ion thermal motion (heating rate) reduces gate fidelity

Experimental data shows that when the number of ions exceeds about 50—100, gate fidelity in a single trap begins to degrade significantly. Therefore, 500+ ion systems must adopt a multi-module architecture.

Photonic Bottleneck of Module Interconnection. Multi-module ion trap quantum computers connect ions in different traps through photon-mediated remote entanglement. The specific process is:

Ions in each module are excited to an optical transition and emit photons
Photons are transmitted through optical fibers to a Bell State Measurement (BSM) station
When BSM succeeds, the ions in the two modules are projected onto an entangled state

The main limitation of current remote entanglement is photon collection efficiency. Photons emitted by ions are distributed over a 4 $\pi$ solid angle, and the numerical aperture of optical collection systems is limited, achieving only about 1—10% collection efficiency. This means the success rate of remote entanglement is extremely low (<1%), and each attempt takes microseconds to tens of microseconds — 2—3 orders of magnitude slower than in-trap gates (~1 $\,\mu\text{s}$ ).

Approaches to improve photon collection efficiency include:

Integrated Optics: Directly integrate fiber couplers or photonic crystal cavities on the ion trap chip
Entanglement Distillation: Generate one high-fidelity entangled pair by consuming multiple low-quality pairs, but this further reduces the effective rate
High-Speed Switch Network: Establish a reconfigurable optical interconnection network to reduce the physical distance and loss to the BSM

Ion Transport Reliability. The QCCD (Quantum Charge-Coupled Device) architecture “transports” ions within the trap by controlling electrode voltages, bringing ions from different regions to an interaction zone to execute two-qubit gates. Transport operations heat the ions (increasing the average quantum number of their motional state), and the current transport error rate is about $10^{-4}$ level. For large-scale algorithms requiring tens of thousands of transports, this error rate must be reduced to below $10^{-6}$ .

Neutral Atom Route: Quantity Lead, Fidelity Catch-Up

Neutral atom platforms lead in qubit count (Atom Computing has achieved 1180-atom arrays), but their gate fidelity has not yet reached the level of other routes.

Physical Limit of Two-Qubit Gate Fidelity. Two-qubit gates in neutral atoms are typically based on the Rydberg blockade effect: when one of two atoms is excited to a Rydberg state, its strong dipolar interaction prevents the neighboring atom from being simultaneously excited. Gate operations are realized through Rabi oscillations, but the Rydberg state has finite lifetime (~100 $\,\mu\text{s}$ ), and atomic thermal motion creates spatial inhomogeneity in interaction strength. Current two-qubit gate fidelity is about 99.5%, while fault-tolerant quantum computing requires >99.9%.

Real-Time Detection and Rearrangement of Atom Loss. Atoms in neutral atom arrays may be lost due to vacuum collisions or photon scattering. In 1000+ atom arrays, the atom loss rate is about $10^{-2}\text{--}10^{-3}$ /second. Lost atoms disrupt the integrity of the error-correcting code because the surface code requires an active physical qubit at every lattice site. The solution is real-time detection (via fluorescence imaging) and atomic rearrangement (using optical tweezers to move reserve atoms to vacant positions), but the rearrangement operation itself takes time (~10—100 $\,\text{ms}$ ), during which the error correction cycle must be paused or compensated.

Silicon Spin Route: CMOS Compatibility vs. Uniformity

Silicon spin qubits use the single electron spin in silicon quantum dots as qubits. Their greatest advantage is CMOS process compatibility — in theory, they can leverage existing semiconductor manufacturing infrastructure for large-scale production.

However, the silicon spin route is currently the smallest in scale (~6—10 qubits), with the core bottleneck being:

Quantum Dot Fabrication Uniformity. The size, potential well depth, and tunnel coupling of each quantum dot are precisely controlled by gate voltages. Nanoscale deviations during fabrication (such as gate width variation and oxide layer thickness non-uniformity) can cause huge differences in the energy level structure of different quantum dots. Currently, each quantum dot requires independent gate voltage calibration, and calibration parameters cannot be reused across different devices. For a 1000+ qubit system, this means initial calibration and continuous drift compensation for over 1000 independent parameters — an engineering problem with no mature solution.

Two-Qubit Gate Speed. Silicon spin two-qubit gates are implemented through the exchange interaction, with gate times of about $10\text{--}100\,\text{ns}$ , comparable to superconducting. However, the exchange interaction is extremely sensitive to quantum dot spacing ( $J \propto e^{-d/a_0}$ , where $a_0$ is the effective Bohr radius), further amplifying the severity of the uniformity problem.

Quantified Metrics: How Many Physical Qubits for an Early Prototype?

Assuming the surface code for quantum error correction, the relationship between the number of logical qubits $n_L$ , code distance $d$ , and physical qubits $n_P$ is:

$n_P \approx 2d^2 \cdot n_L$

The factor of 2 comes from the surface code encoding both $X$ -type and $Z$ -type stabilizers. For $d=15$ (logical error rate on the order of $10^{-6}$ ), each logical qubit requires about 450 physical qubits.

If an early prototype can run a simplified version of Shor’s algorithm (such as factoring 15 or 21) or small quantum simulation problems, it requires about 10—20 logical qubits. Considering the overhead of magic state distillation and ancilla qubits (roughly an additional 30—50%), the total number of physical qubits is approximately:

$n_P \approx 2 \times (15)^2 \times 20 \times 1.5 \approx 13{,}500$

This is a conservative estimate. If the code distance needs to increase to $d=25$ for lower logical error rates, or if the number of logical qubits increases to 50—100, the physical qubit count will exceed 100,000.

A more realistic definition of an “early prototype” is: capable of running a useful quantum algorithm (such as 20-qubit quantum simulation or simplified Shor), with a physical qubit requirement of about 1000—2000 (corresponding to $d=7\text{--}11$ surface code, accepting higher logical error rates and averaging over multiple runs). This order of magnitude is a target that current platforms can hope to reach within 3—5 years.

Summary: The superconducting route faces a triple dilemma of fabrication yield (needs improvement from 80-90% to 99.9%+), wiring thermal load (3000 cables vs. cooling power gap of 3 orders of magnitude), and crosstalk suppression ( $ZZ$ coupling worsens exponentially with density). The ion trap route is limited by single-trap phonon spectral density (56 ions is close to the limit), multi-module interconnects with only 1-10% photon collection efficiency, and QCCD transport error rates that need to drop from $10^{-4}$ to $10^{-6}$ . The neutral atom route leads in quantity (1000+) but lags in two-qubit gate fidelity (~99.5%), with real-time rearrangement of lost atoms as an open problem. The silicon spin route has the strongest CMOS compatibility, but quantum dot uniformity keeps it at the smallest current scale (~6—10 qubits), and two-qubit gate speed is limited by the exponential sensitivity of the exchange interaction. An early prototype requires about 1000—2000 high-quality physical qubits ( $d=15\text{--}25$ surface code + magic state overhead), an order of magnitude that demands simultaneous breakthroughs in fabrication, control, and interconnection across all platforms.

Connection to Quantum Computing: Qubit scaling is not simply “copy-pasting” 100 qubits into 1000. The mathematical guarantees of error-correcting codes (such as the threshold theorem for the surface code) assume that all physical qubits are homogeneous and independent, but in engineering reality, fabrication non-uniformity, thermal load, and crosstalk break these assumptions. The stabilizer code theory discussed in Chapter 4 holds under ideal conditions, but when scaling to the thousand-qubit level, every Josephson junction’s $E_J$ deviation, every cable’s thermal load, and every ion transport’s heating are the friction that translates mathematical theorems into engineering reality. Understanding these scaling obstacles is a necessary step in mapping quantum error correction from theoretical concepts to foundries, dilution refrigerators, and optical tables. Without 1000+ homogeneous qubits, there are no fault-tolerant logical qubits; without fault-tolerant logical qubits, there are no general-purpose quantum algorithms.

6.3 Universal Fault-Tolerant Gates: From Clifford to Clifford+T

The Current Logic Gate Gap

Quantinuum H2 demonstrated the complete set of logical Clifford gates (Hadamard $H$ , Phase $S$ , CNOT), an important milestone in fault-tolerant quantum computing. However, Clifford gates themselves do not constitute universal quantum computing — according to the Gottesman-Knill theorem (Section 4.5), purely Clifford circuits can be efficiently simulated classically. To achieve the theoretical advantage of quantum computing, non-Clifford gates must be introduced.

In the standard gate set, the minimal universal set is Clifford + $T$ gate, where the $T$ gate ( $\pi/8$ gate) is defined as:

$T = \begin{pmatrix} 1 & 0 \\ 0 & e^{i\pi/4} \end{pmatrix}$

The $T$ gate does not belong to the Clifford group, because it transforms Pauli operators beyond the Pauli group:

$TXT^\dagger = e^{-i\pi/4}SX$

This “non-stabilizer” property makes the $T$ gate the key to achieving universal quantum computing, but it is also precisely why it cannot be “transparently” embedded into stabilizer error-correcting codes like Clifford gates can.

As of 2025, no platform has completed a fault-tolerant demonstration of the logical $T$ gate. Willow has not yet reached the logical Clifford gate stage; Quantinuum H2 has distilled logical $|T\rangle$ states, but has not yet fully integrated them into a controlled logical $T$ gate and verified the error rate.

Why Logical $T$ Gates Are Harder Than Clifford Gates

Transversality of Clifford Gates. Clifford gates ( $H$ , $S$ , CNOT) map Pauli operators to Pauli operators in the Heisenberg picture. This means:

In stabilizer codes, Clifford gates can be implemented transversally: each physical qubit independently receives the same single-qubit Clifford gate, or physical CNOTs directly correspond to logical CNOTs
Transversal implementation is inherently fault-tolerant: a single physical gate error only affects one physical qubit and does not propagate into multiple logical errors

Non-Transversality of $T$ Gates. The Eastin-Knill theorem rigorously proves: no non-trivial quantum error-correcting code can transversally implement a universal quantum gate set. Specifically for the $T$ gate, it cannot be realized through a simple transversal physical $T$ gate. Alternative approaches must be used:

Approach 1: Gate Teleportation

Using pre-prepared entangled resource states and Bell measurements to realize the logical $T$ gate. The specific process is:

Pre-prepare an auxiliary logical qubit in the state $|A\rangle = T|+\rangle$ (or an equivalent state)
Execute a CNOT and $H$ measurement on the target logical qubit and the auxiliary qubit
Apply corrective Clifford gates based on the measurement results

The fault-tolerance of gate teleportation depends on the quality of the auxiliary state $|A\rangle$ . If $|A\rangle$ has errors, the errors will propagate to the target qubit through measurement. Therefore, the auxiliary state must have extremely low error rates.

Approach 2: Magic State Injection

Directly prepare a high-quality logical $|T\rangle = T|+\rangle$ state, then consume it through gate teleportation to realize the $T$ gate. The quality (fidelity) of the magic state determines the error rate of the logical $T$ gate.

Approach 3: Code Deformation / Lattice Surgery

Realize an equivalent logical $T$ gate by changing the boundary conditions of the surface code or merging/splitting code blocks. This method avoids explicit magic state preparation, but requires complex real-time decoding support and has higher error correction overhead.

Error Rate Target for Logical $T$ Gates

The logical $T$ gate is the most expensive resource in universal quantum computing. Its error rate must satisfy:

$\epsilon_T \lesssim \epsilon_{\text{storage}}$

where $\epsilon_{\text{storage}}$ is the storage error rate of the logical qubit (i.e., the error rate with only storage error correction). If $\epsilon_T > \epsilon_{\text{storage}}$ , then executing the $T$ gate will dominate the logical error, and the storage advantage of the error-correcting code will be negated.

Taking Willow’s $d=7$ surface code as an example, the storage logical error rate is about $8 \times 10^{-6}$ . Therefore, the logical $T$ gate error rate should be below about $10^{-6}$ .

More strictly, for algorithms requiring $N_T$ $T$ gates (such as Shor 2048-bit RSA requiring about $10^9$ $T$ gates), the total $T$ gate error rate must satisfy:

$N_T \cdot \epsilon_T \ll 1$

This means that for large-scale algorithms, $\epsilon_T$ needs to reach $10^{-9}$ or lower — which typically requires two levels of magic state distillation (Section 6.4).

Logical $T$ Gate Paths by Platform

Superconducting (Google/IBM/Rigetti): Currently no logical gate demonstration. The path is to implement logical Clifford gates through surface code lattice surgery, while building on-chip magic state factories for distillation. First demonstration expected in 2027—2028.

Ion Trap (Quantinuum): Already demonstrated logical Clifford gates and one level of magic state distillation. The next step is to integrate the distilled logical $|T\rangle$ state into the gate teleportation process and verify the logical $T$ gate error rate. Due to the long coherence time of ion traps ( $T_2 \sim 1\text{--}10\,\text{s}$ ), the number of gates per error correction cycle is much larger than for superconducting, with slower logical gate speed but higher fidelity.

Neutral Atoms: Not yet at the logical gate stage. They first need to improve two-qubit gate fidelity from 99.5% to 99.9%+, then construct storage error correction demonstrations using the surface code or color code.

Summary: Quantinuum H2 has demonstrated the complete set of logical Clifford gates, but the fault-tolerant demonstration of the $T$ gate remains a global gap. The non-Clifford nature of the $T$ gate prevents transversal implementation, requiring gate teleportation or magic state injection. The logical $T$ gate error rate must be below the storage logical error rate (about $10^{-6}$ ), while large-scale algorithms (such as Shor 2048-bit) require $10^{-9}$ or lower, typically needing two levels of magic state distillation. Among platforms, ion traps are closest to the target, superconducting is expected to demonstrate in 2027—2028, and neutral atoms and silicon spin are at earlier stages.

Connection to Quantum Computing: The stabilizer theory and Gottesman-Knill theorem established in Chapter 4 tell us: Clifford gates are insufficient for quantum advantage; non-Clifford resources must be introduced. The magic state distillation discussed in Section 4.8 is precisely the mechanism that provides high-quality resources for logical $T$ gates. The engineering realization of the logical $T$ gate is the critical step in transforming the “Clifford+T universality” theorem into a runnable algorithm. Without a fault-tolerant logical $T$ gate, even with thousands of physical qubits and a perfect real-time decoder, the computer can only execute classically simulable Clifford circuits — it cannot factor large integers or simulate strongly correlated quantum systems. The logical $T$ gate is the weakest link between the theory and practice of universal quantum computing.

6.4 Magic State Distillation at Scale

Quantinuum’s 2025 logical magic state distillation demonstration was a proof of principle: it proved that the 15-to-1 distillation protocol can be applied at the logical level to purify low-quality physical magic states into higher-quality logical magic states. However, between “being able to distill one state” and “industrial-scale production of magic states to support general algorithms,” there is a yield gap spanning several orders of magnitude.

Quantitative Analysis of Distillation Overhead

Bravyi-Haah and Reed-Muller Protocols. The most commonly used magic state distillation protocol is based on the 15-to-1 protocol from Reed-Muller error-correcting codes: consuming 15 input magic states (fidelity $F_{\text{in}}$ ) to produce 1 output magic state (fidelity $F_{\text{out}}$ ). The fidelity improvement satisfies:

$1 - F_{\text{out}} \approx 35(1 - F_{\text{in}})^3$

This relationship means: if the input fidelity $F_{\text{in}} = 0.999$ (i.e., error rate $10^{-3}$ ), the output fidelity is about $1 - 35 \times 10^{-9} \approx 0.999999965$ (error rate about $3.5 \times 10^{-8}$ ).

For large-scale algorithms requiring $10^{-9}$ output error rate, a single level of 15-to-1 protocol is insufficient, requiring two levels of distillation:

Level 1: 15 physical $|T\rangle$ states (error rate $10^{-3}$ ) → 1 level-1 $|T\rangle$ state (error rate $10^{-8}$ )
Level 2: 15 level-1 $|T\rangle$ states (error rate $10^{-8}$ ) → 1 level-2 $|T\rangle$ state (error rate $<10^{-9}$ )

The total overhead of two-level distillation is $15 \times 15 = 225$ physical magic states to produce one usable magic state.

Algorithm-Level $T$ Gate Requirements. Shor 2048-bit RSA factorization requires about $10^9$ $T$ gates (depending on specific circuit optimization). With two-level distillation:

$N_{\text{physical}} = 225 \times 10^9 = 2.25 \times 10^{11}$

That is over 200 billion physical magic states. Even if each physical magic state takes only $1\,\mu\text{s}$ to prepare, the total time would exceed 6 years — clearly unacceptable.

This absurd result reveals the limitations of the current approach and motivates two optimization directions:

Protocol Optimization: Use more efficient distillation protocols. For example, the Bravyi-Haah protocol can achieve lower output error rates at the same input fidelity, or reduce the number of required input states. The latest research has reduced the effective overhead to about 50—100:1 (compared to 225:1 for 15-to-1).
Physical-Layer Fidelity Improvement: If physical $T$ gate fidelity can be increased from 99.9% to 99.99% (error rate from $10^{-3}$ to $10^{-4}$ ), a single level of distillation can achieve $10^{-9}$ output error rate, reducing total overhead to 15:1.

Chip Architecture for Magic State Factories

In an actual fault-tolerant quantum computer, magic states are not prepared on demand; they are produced on a pipeline by a dedicated Magic State Factory.

Spatial Overhead. The magic state factory needs to occupy a dedicated area on the chip. Using the surface code as an example, the preparation and distillation of each physical magic state requires about $d^2$ physical qubits (for encoding and ancilla). For two-level distillation, one factory requires approximately:

$A_{\text{factory}} \sim 2d^2 \times (15 + 15) = 60d^2$

physical qubits (assuming 15 level-1 factories feeding one level-2 factory in parallel). When $d=15$ , this is about 13,500 physical qubits. This means the magic state factory may occupy 30—50% of the total chip area.

Temporal Overhead and Pipelining. Each distillation protocol requires multiple error correction cycles to complete (measure stabilizers, decode, apply corrections). The 15-to-1 protocol requires about $O(d)$ error correction cycles. When $d=15$ and the error correction cycle is $1\,\mu\text{s}$ (superconducting), a single factory’s yield rate is approximately:

$R \sim \frac{1}{15 \times 1\,\mu\text{s}} \approx 6.7 \times 10^4 \,\text{states/s}$

This is far below the algorithmic requirements. The solution is parallelization: deploy tens to hundreds of magic state factories on the chip, routing the produced magic states to the computation area through a bus network.

Error Accumulation in Bus Transport. The transport of magic states from the factory to the computation area requires moving across the chip through SWAP gate sequences or chain teleportation. Each transport operation introduces additional errors, potentially negating the distillation gains. Therefore, magic state factories need to be as close as possible to the computation area, or the transport path itself needs error correction protection.

Key Metric: Magic States/Second

Summarizing the above analysis, industrial-scale magic state distillation needs to meet the following metrics:

Metric	Current Demo	Early Prototype Requirement	Practical Quantum Computing Requirement
Single physical $T$ gate error rate	$10^{-3}$	$10^{-4}$	$10^{-4}$
Distillation levels	1 (proof of principle)	1—2	1—2
Effective yield (physical:logical)	15:1	15—100:1	15—50:1
Total yield (states/s)	$<10^3$	$>10^6$	$>10^9$
Factory chip area fraction	N/A	30—50%	20—30%

A yield of $10^6$ states/s corresponds to about 100 parallel factories (each producing $10^4$ /s), which is feasible for an early prototype with 1000—2000 physical qubits. However, $10^9$ states/s would require a large-scale parallel factory network on a million-qubit chip.

Summary: Quantinuum’s 2025 logical magic state distillation was a proof-of-principle breakthrough, but general-purpose quantum computing requires millions of high-fidelity magic states per minute. The 15-to-1 protocol consumes 15 inputs to produce 1 output; two-level distillation from $10^{-3}$ input error rate to $<10^{-9}$ output error rate requires 225 physical states for 1 logical state. Shor 2048-bit RSA’s need for $10^9$ $T$ gates implies a total consumption of over 200 billion physical magic states — unacceptable on the current path. Optimization directions include more efficient protocols (Bravyi-Haah, reducing effective overhead to 50—100:1) and physical-layer fidelity improvement (from 99.9% to 99.99%, enabling single-level distillation to meet the target). The magic state factory would occupy 30—50% of the chip area, achieving $>10^6$ states/s yield through parallelization. From “being able to distill” to “industrial-scale production,” the gap is roughly 6 orders of magnitude in yield.

Connection to Quantum Computing: Section 4.8 argued from a resource-theoretic perspective that magic states are the “currency” of quantumness — Clifford operations are “free,” and non-Clifford resources are expensive. Magic state distillation is the only known path to convert this theoretical resource into engineering resources. The realization of the logical $T$ gate (Section 6.3) depends on the supply of magic states, and the supply of magic states is limited by chip area, error correction cycle, and transport losses. This dependency chain reveals a profound engineering reality: the speed bottleneck of general-purpose quantum computing may not be qubit count or decoding latency, but the yield of the magic state factory. Understanding the quantitative overhead of magic state distillation is the core parameter for assessing whether a quantum computer can run useful algorithms within a reasonable time.

6.5 Real-Time Decoders: From FPGA to ASIC

Quantum error correction is not a “post-mortem analysis” — it must complete the full closed loop of syndrome measurement, error decoding, and corrective feedback within the qubit coherence time. As the qubit scale expands from 100 to 1000+, the computational complexity and data bandwidth of the decoder will become system bottlenecks.

Computational Complexity of the Decoding Problem

Syndrome Data Volume. For a surface code with $n$ physical qubits, each error correction cycle requires measuring $O(n)$ stabilizer generators (roughly half $X$ -type and half $Z$ -type). Taking the $d=15$ surface code as an example, it requires about 225 data qubits and 224 ancilla qubits for stabilizer measurements, producing about 448 syndrome bits per cycle.

For a system with 1000 physical qubits (about 4—5 logical qubits, $d\approx 15$ ), the syndrome data per cycle is about $10^3$ bits. If the error correction cycle is $1\,\mu\text{s}$ (superconducting), the syndrome data rate is $10^9$ bits/second — already approaching the I/O bandwidth limit of FPGAs.

Decoding Algorithm Complexity. Minimum Weight Perfect Matching (MWPM) is the most commonly used decoding algorithm for the surface code. Its time complexity is:

$T_{\text{decode}} = O(d^3 \cdot \alpha(d))$

where $\alpha(d)$ is the inverse Ackermann function (approximately constant). For $d=15$ , $T_{\text{decode}} \approx O(3375)$ basic operations. On an FPGA, MWPM latency is about $1\text{--}10\,\mu\text{s}$ — acceptable for $d=15$ , but for $d=25$ ( $O(15625)$ operations), the latency would increase to tens of microseconds.

More advanced decoding algorithms (such as Union-Find, Belief Propagation, or Neural Network Decoders) may have better asymptotic complexity as $d \to \infty$ , but in the practical $d=15\text{--}25$ range, MWPM remains one of the best choices for the trade-off between latency and error rate.

The Race Between Latency and Coherence Time

Decoding latency must satisfy:

$t_{\text{decode}} + t_{\text{control}} + t_{\text{feedback}} \ll T_2 / D$

where $D$ is the logical gate depth executed within the error correction cycle, and $T_2$ is the qubit coherence time.

For the superconducting route:

$T_2 \sim 30\text{--}100\,\mu\text{s}$
Error correction cycle $\sim 1\,\mu\text{s}$ (including measurement, reset, gate operations)
Target $D \sim 10\text{--}100$ (i.e., 10—100 error correction cycles per $T_2$ )
Therefore total feedback latency must be $<100\,\text{ns}$ , ideally $<10\,\text{ns}$

Current FPGA decoder latency is about $1\text{--}10\,\mu\text{s}$ , which is 2—3 orders of magnitude slower than the requirement. This gap means: current systems cannot complete the real-time error correction closed loop within the coherence time of superconducting qubits, forcing the error correction cycle to be extended (reducing effective gate speed) or accepting higher logical error rates (because errors are not corrected during the latency period).

For the ion trap route:

$T_2 \sim 1\text{--}10\,\text{s}$
Error correction cycle $\sim 1\,\text{ms}$ (slow gate speed, but long coherence time)
Target $D \sim 10^3\text{--}10^4$
Total feedback latency must be $<100\,\mu\text{s}$ , ideally $<1\,\text{ms}$

The “slow pace” of ion traps provides a more generous time window for the decoder, but it also means that algorithm execution speed is far lower than superconducting.

The Inevitability of Moving from FPGA to ASIC

Bandwidth and Power Limitations of FPGAs. FPGAs (Field-Programmable Gate Array) are the current standard platform for quantum error correction decoders (such as the decoder used by Google Willow). The advantages of FPGAs are flexibility and short development cycles, but their limitations are:

Limited clock frequency (typically <500 MHz)
Limited on-chip memory and logic resources
Higher power consumption (typical FPGA power 10—50 W, while a dilution refrigerator’s cooling power at the 4K stage is only about 1 W)

For 1000+ qubit systems, FPGAs cannot meet the latency and power requirements. It is necessary to transition to ASIC (Application-Specific Integrated Circuit).

ASIC Decoder Requirements:

Metric	FPGA (Current)	ASIC (Requirement)
Decoding latency	$1\text{--}10\,\mu\text{s}$	$<1\,\mu\text{s}$ (superconducting) or $<1\,\text{ms}$ (ion trap)
Syndrome data bandwidth	$10^8\text{--}10^9$ bps	$>10^{10}$ bps
Power consumption	10—50 W	$<1\,\text{W}$ (dissipatable at 4K stage)
Chip area	Large (commercial board)	$<1\,\text{cm}^2$ (integrated at cryogenic stage)
Logical qubit support	1—5	10—100+

Cryo-CMOS and Near-Quantum Computing. The ideal decoder should be integrated at the cryogenic stage (1—4K), or even closer to the qubits (100 mK level), to reduce signal transmission latency and thermal load. Cryo-CMOS technology is mature at the 4K level, but faces challenges of carrier freeze-out and threshold voltage drift at the 100 mK level. Both Google and Intel are investing in cryo-CMOS control electronics, with prototype chips expected in 2026—2028.

Distributed Decoding Architecture

For larger-scale systems ( $>100$ logical qubits), a single decoder cannot process the global syndrome data. A hierarchical decoding architecture is required:

Fast Local Decoding + Slow Global Decoding:

Local Layer: Each $d \times d$ physical block is equipped with a dedicated micro-decoder (ASIC) that processes only the local syndrome of that block, with latency $<100\,\text{ns}$ , correcting local errors
Global Layer: A central decoder handles cross-block syndrome correlations and logical error chains, with latency $<10\,\mu\text{s}$ , correcting non-local errors

This architecture exploits the locality of surface code errors — most errors are local, and only a few error chains span long distances. The local layer handles over 99% of errors, and the global layer only processes the remaining long-range correlations.

Potential of Neural Network Decoders. Recent research has explored using deep neural networks (DNNs) to replace MWPM for decoding. The advantages of DNNs are:

Extremely low forward propagation latency ( $<100\,\text{ns}$ , if implemented on a dedicated ASIC)
Can learn the non-Markovian nature and spatial correlations of noise
But as $d$ increases, training data requirements and generalization ability remain open problems

DNN decoders are still in the research stage and have not yet been validated on real hardware to confirm that their error rates are not worse than MWPM.

Summary: A 1000+ qubit surface code produces about $10^3$ syndrome bits per cycle, with a data rate of $10^9$ bps at $1\,\mu\text{s}$ error correction cycle. MWPM decoding complexity is $O(d^3)$ , with FPGA latency of $1\text{--}10\,\mu\text{s}$ , while the superconducting route requires $<100\,\text{ns}$ — a gap of 2—3 orders of magnitude. FPGA power consumption (10—50 W) also far exceeds the dilution refrigerator’s cooling capacity at the 4K stage (~1 W). A transition to ASIC decoders is necessary, targeting latency of $<1\,\mu\text{s}$ (superconducting) or $<1\,\text{ms}$ (ion trap), and power consumption $<1\,\text{W}$ . Cryo-CMOS is the direction for integration, but process challenges remain at the 100 mK level. Large-scale systems require a distributed two-layer architecture (fast local + slow global), and neural network decoders have potential but are not yet mature. The decoder is the most easily underestimated bottleneck in the quantum error correction closed loop.

Connection to Quantum Computing: The quantum error correction theory discussed in Chapter 4 assumes “perfect syndrome measurement and instantaneous decoding.” In engineering reality, measurements themselves have errors ( $\sim 1\%$ ), decoding takes tens of microseconds, and feedback signals experience cable transmission delays. These “non-idealities” reduce the surface code’s theoretical threshold ( $\sim 1\%$ ) to an actual effective threshold ( $\sim 0.1\text{--}0.5\%$ ). The decoder is not a “peripheral device” of quantum computing — it is the core link in the error correction closed loop, and its latency directly determines the effective error correction cycle and logical gate speed. Without a real-time decoder, the surface code is just a static quantum memory; with a real-time decoder, it becomes a dynamic computing engine. Understanding the engineering constraints of the decoder is the key to understanding why “below threshold” is just the starting point, not the finish line.

6.6 Cryogenic and Control System Integration

A quantum computer is not an isolated array of qubits — it is a system integration engineering effort involving extreme cryogenics, microwave/laser control, high-speed classical computing, and precision calibration. Moving from laboratory demonstrations to engineering systems requires crossing three dimensions: stability, integration density, and automation.

Current Demonstration vs. Early Prototype: System-Level Comparison

Dimension	Current Demo	Early Prototype Requirement
Operational stability	Hours to days	Continuous weeks
Control electronics	Stacked commercial instruments (Keysight/Rohde & Schwarz)	Custom ASIC + Cryo-CMOS
Wiring thermal load	Dozens of coaxial cables to 10 mK	Thousands -> HTS interconnects or multiplexing
Auto-calibration	Manual or semi-automatic (<100 parameters)	Fully automatic (>1000 parameters, hourly updates)
Quantum-classical interface	FPGA/software backend	Dedicated ASIC/near-memory computing
Operating environment	Dedicated lab, 24/7 staffed	Standard data center, remote operation
Mean time between failures (MTBF)	Hours	>1000 hours

Core Contradiction: The 3-Orders-of-Magnitude Gap Between Heat Load and Cooling Power

Each qubit requires 2—3 control lines (XY microwave, Z DC/RF, readout). For 1000 qubits:

Total control lines: 2000—3000
Thermal load per coaxial cable (from 300K to 10 mK): 10—100 $\,\mu\text{W}$ (depending on material and diameter)
Total thermal load: 20—300 $\,\text{mW}$

Commercial dilution refrigerators (such as Bluefors LD400 or Oxford Instruments Triton) have a cooling power at the 10 mK stage of:

10—100 $\,\mu\text{W}$

There is a 3-orders-of-magnitude gap between the total thermal load (20—300 mW) and the cooling power (10—100 $\mu$ W). This contradiction is one of the most fundamental physical limitations on superconducting quantum computing scalability.

Technical Solution Paths:

Cryo-CMOS Multiplexing: Integrate CMOS control chips at the 4K stage or lower，converting digital control signals into analog microwave/RF pulses, reducing the number of analog signal lines entering the 10 mK stage from room temperature. For example, a 64:1 multiplexer can reduce 3000 lines to about 50. Cryo-CMOS has been preliminarily demonstrated at the 4K level, but faces challenges of carrier freeze-out and device characteristic drift at the 100 mK level.
HTS Interconnects: Use high-temperature superconducting materials (such as YBCO, critical temperature ~90K) as intermediate transmission lines. HTS wires are resistance-free above liquid nitrogen temperature (77K), significantly reducing heat conduction from 300K to 4K. However, process compatibility between HTS and low-temperature superconducting qubits (such as material contamination and interface losses) remains a research topic.
3D Packaging and On-Chip Integration: Directly integrate control electronics onto the back side or adjacent layers of the qubit chip, connected through through-silicon vias or micro-bumps. This approach minimizes external wiring but places extremely high demands on chip design and thermal management. through through-silicon vias or micro-bumps. This approach minimizes external wiring but places extremely high demands on chip design and thermal management. through through-silicon vias (TSVs) or micro-bumps. This approach minimizes external wiring but places extremely high demands on chip design and thermal management.
Optical Links: Replace some coaxial cables with optical fibers for transmitting control signals. Optical fibers have much lower thermal conductivity than metals and extremely high bandwidth. The challenge is that converting optical signals to microwave signals that qubits can respond to requires optoelectronic converters, whose efficiency and noise characteristics at cryogenic temperatures are not yet mature.

Custom ASIC Requirements for Control Electronics

The current control layer of quantum computers relies on commercial RF instruments (arbitrary waveform generators, vector signal generators, digital acquisition cards), which:

Are bulky (filling multiple racks)
Have high power consumption (tens of watts per channel)
Are expensive (tens of thousands of dollars per channel)
Have uncertain latency (software-triggered, ms-level jitter)

An early prototype requires custom control ASICs, with the following specifications:

Power consumption per channel $<10\,\text{mW}$ (cryogenic-stage integration)
Waveform update rate $>1\,\text{GS/s}$ (supporting nanosecond-level pulse shaping)
Phase coherence (phase jitter between channels $<0.1^\circ$ )
Real-time feedback (from measurement to next pulse $<100\,\text{ns}$ )

Google, IBM, and Intel have all initiated cryogenic control ASIC projects, with engineering samples expected in 2026—2028.

Auto-Calibration: From Hundreds to Thousands of Parameters

The tunable parameters of a 1000+ qubit system include:

Each qubit’s frequency, drive power, pulse shape (~5—10 parameters/qubit)
Each readout resonator’s frequency, coupling strength (~3—5 parameters/readout)
Each coupler’s bias voltage (~1—2 parameters/coupler)
Global parameters: temperature, magnetic field, microwave source phase reference

Total >5000 parameters, and these parameters drift over time (thermal cycling, magnetic field fluctuations, charge noise). Manual calibration is impossible; a fully automatic calibration system is required:

Calibration Process:

Initial Calibration: Determine rough parameters for each qubit through fast sweeping
Fine Calibration: Execute single/two-qubit gate tomography (GST/Randomized Benchmarking) to optimize fidelity
Drift Tracking: Monitor parameter drift through intermittent probe pulses
Adaptive Correction: Predict and pre-compensate based on drift models

The current state-of-the-art in auto-calibration (such as IBM’s Qiskit Pulse and Google’s optimization pipeline) can handle about 100 qubits, but scaling to 1000+ qubits requires machine learning-driven parameter inference and distributed parallel calibration.

Summary: A 1000-qubit superconducting system requires 2000—3000 control lines, with a total thermal load of 20—300 mW, while the dilution refrigerator has a cooling power of only 10—100 $\mu$ W at the 10 mK stage — a 3-orders-of-magnitude gap. Solutions include Cryo-CMOS multiplexing (mature at 4K, challenging at 100 mK), HTS interconnects (process compatibility to be resolved), 3D packaging, and optical links. Control electronics must transition from commercial instruments to custom ASICs, targeting <10 mW per channel, >1 GS/s waveform update rate, and <100 ns feedback latency. Auto-calibration needs to scale from the current <100 parameters to >1000 parameters, using machine learning for real-time drift tracking and adaptive correction. Operational stability needs to improve from hours to continuous weeks, and MTBF from hours to >1000 hours. The cryogenic/control system is not a “supporting facility” for quantum computing — it is the core engineering bottleneck that determines the upper limit of scale.

Connection to Quantum Computing: The preceding chapters discussed the abstract theories of qubits, quantum gates, and error-correcting codes from mathematical and physical perspectives. This section’s analysis of the cryogenic/control system reveals an engineering truth: the speed, scale, and reliability of quantum computing are ultimately determined by classical engineering systems. The cooling power of the dilution refrigerator, the thermal conductivity of coaxial cables, the threshold voltage drift of CMOS transistors at 4K — these classical physical quantities set the boundaries of quantum computing. No matter how long the qubit $T_2$ time is, if control pulses become misaligned due to temperature drift, the effective coherence time will be shortened; no matter how high the surface code’s error correction threshold is, if the decoder latency exceeds the error correction cycle, the logical error rate will spiral out of control. Understanding the integration challenges of the cryogenic/control system is the key perspective shift in reframing quantum computing from a “physics experiment” to a “systems engineering” endeavor.

6.7 Logical Qubit Interconnect and Efficient Codes

Even after solving the problems of physical qubit scaling, the complete set of logical gates, magic state distillation, and real-time decoding, an early prototype still faces a fundamental efficiency bottleneck: the ratio of physical qubits to logical qubits.

Physical Qubit Overhead of the Surface Code

The surface code is currently the most promising quantum error correction scheme, with a physical qubit overhead of:

$n_P = 2d^2 \cdot n_L$

For code distance $d=15$ (logical error rate about $10^{-6}$ ), the ratio is $2 \times 225 = 450:1$ . That is, 450 physical qubits encode 1 logical qubit. For $d=25$ (logical error rate about $10^{-10}$ ), the ratio is $1250:1$ .

This overhead is acceptable for an early prototype (10—20 logical qubits, about 5000—25,000 physical qubits), but for practical quantum computing (1000+ logical qubits), it means hundreds of millions of physical qubits — far beyond any known manufacturing capability.

Quantum LDPC Codes: Theoretical Hope for Reducing Overhead

Low-Density Parity-Check (LDPC) codes are a key technology in classical error correction for approaching the Shannon limit. Quantum LDPC codes extend this idea to the quantum domain, with the goal of:

Maintaining bounded stabilizer weight (each stabilizer involves only a constant number of physical qubits)
Achieving a constant ratio of $n_P / n_L = O(1)$ , rather than the surface code’s $O(d^2)$

In theory, good quantum LDPC codes can reduce the physical qubit ratio from $450:1$ to about $10:1$ or even lower. This means 1000 logical qubits would require only about 10,000 physical qubits — a number within reach of current technology.

However, the physical implementation of quantum LDPC codes faces major challenges:

Non-Nearest-Neighbor Connectivity Requirements. The advantage of the surface code is that it only requires nearest-neighbor connections on a 2D grid (each qubit is coupled to only 4 neighbors). Most quantum LDPC codes require long-range connections — some stabilizers may involve physical qubits separated by tens or hundreds of positions. On superconducting chips, long-range connections require microwave buses or multi-layer wiring across the chip, introducing additional crosstalk and loss. Ion trap and neutral atom platforms, with their inherent all-to-all connectivity or reconfigurable geometry, have a potential advantage in implementing LDPC codes.

Decoding Complexity. Decoding of LDPC codes is typically based on Belief Propagation (BP), with time complexity $O(n)$ , but requiring iterative convergence. For quantum LDPC codes, BP may fail due to short cycles in the parity check matrix, requiring combination with Ordered Statistics Decoding (OSD), which increases latency and computational overhead.

Current Progress. In 2023—2024, research teams including Panteleev-Kalachev and Leverrier proposed quantum LDPC code constructions with good parameters ( $n_P/n_L \sim 20\text{--}50$ , code distance $d \sim \sqrt{n}$ ). However, whether the threshold (the upper bound of single-qubit error rate tolerance) of these codes reaches or exceeds the surface code’s ~1% remains an open question. Furthermore, the physical implementation schemes (how to route these codes on specific hardware) are not yet mature.

Logical Qubit Interconnection: Bus Transport and Error Correction

In a multi-logical-qubit quantum computer, logical qubits need to execute CNOT or other two-logical-qubit gates. In the surface code, this is achieved through Lattice Surgery or Code Deformation, which essentially involves temporarily merging the boundaries of two logical qubits, performing an operation, and then separating them.

When the number of logical qubits increases, they cannot all be adjacent to each other. Information of logical qubits needs to be transmitted across the chip through a “Bus.”

Bus Transport Issues. On superconducting chips, logical qubit information is transmitted hop-by-hop between physical qubits through SWAP gate chains. Each SWAP is a set of physical two-qubit gates, introducing additional opportunities for errors. If the physical qubit error rate on the transmission path is not corrected, logical information may suffer irreversible errors before reaching the destination.

Bus-Level Error Correction. The solution is to also apply error correction protection on the transmission path — i.e., the bus itself is encoded with the surface code. This means the chip needs not only the “computation region” (holding logical qubits) and the “magic state factory,” but also a “communication region” (for moving and interconnecting logical qubits). This further increases the total number of physical qubits required.

Modular Architecture. For very large-scale systems ( $>100$ logical qubits), a single-chip solution may be infeasible, requiring a modular architecture: each module contains several logical qubits and a local magic state factory, with modules interconnected through quantum links (photonic, phononic, or superconducting coupling). The communication latency and error rate of the modular architecture will become new system bottlenecks.

Summary: The surface code’s physical-to-logical qubit ratio is $2d^2:1$ , about 450:1 at $d=15$ , meaning billions of physical qubits for 1000 logical qubits — unacceptable. Quantum LDPC codes can theoretically reduce the ratio to ~10:1, requiring only about 10,000 physical qubits for 1000 logical qubits, but they require non-nearest-neighbor connections (difficult for superconducting, advantageous for ion traps/neutral atoms), and the threshold and physical implementation schemes remain open problems. Logical qubit interconnection requires bus transport, where SWAP chains introduce additional errors, requiring the bus itself to have error correction protection, further increasing area overhead. Modular architecture is the inevitable choice for very large-scale systems, but the latency and error rate of inter-module quantum links will become new bottlenecks. The transition from the surface code to LDPC codes is the key leap for fault-tolerant quantum computing from “can work” to “is efficient.”

Connection to Quantum Computing: The stabilizer code theory introduced in Chapter 4 centers on the surface code because it has the optimal threshold and simplest physical implementation under 2D nearest-neighbor constraints. But this section’s analysis reveals an engineering reality: the simplicity of the surface code comes at the cost of an exponential physical qubit overhead. LDPC codes represent the next frontier of error correction theory — dramatically reducing physical overhead while maintaining fault tolerance. This transition is not just a matter of error-correcting code selection; it profoundly impacts hardware architecture: platforms that support LDPC codes (such as the all-to-all connectivity of ion traps and the reconfigurable geometry of neutral atoms) may surpass the superconducting 2D grid in long-term scalability. Understanding the interplay between error-correcting code efficiency and physical platform connectivity constraints is key to predicting the divergence of future quantum computing technology roadmaps.

6.8 Timeline and Roadmap: Not a Prophecy, But an Engineering Checklist

The preceding sections analyzed the seven engineering milestones from the current state to early prototypes. This section integrates these milestones into a timeline and clarifies the prerequisites for each. It must be emphasized: this is not an optimistic prophecy of future technological breakthroughs, but an engineering dependency graph — the credibility of each time point depends on the completion of its predecessor milestones.

Key Milestones and Timeline

Milestone	Expected Time	Dependencies	Primary Platforms
100 logical qubits + full Clifford gates	2027—2028	Chip scale expansion to 200—500 qubits; logical gate integration technology mature	Superconducting (Google/IBM), Ion Trap (Quantinuum)
Logical $T$ gate error $<10^{-6}$	2028—2029	Industrial magic state distillation; real-time decoding latency $<1\,\mu\text{s}$	Ion Trap (leading), Superconducting (catching up)
Early prototype (fault-tolerant Shor/quantum simulation)	2030—2033	All above milestones integrated; 1000—2000 physical qubits; continuous operation >1 week	Multi-platform competition
Practical quantum computing (breaking RSA-2048)	2035+	Million physical qubit scale; logical error rate $<10^{-10}$ ; magic state yield $>10^9$ /s	Uncertain

Milestone 1: 100 Logical Qubits + Full Clifford Gates (2027—2028)

This is the first step from “storage error correction” to “dynamic computation.” Requirements:

Superconducting: Scale from 105 qubits (Willow) to 500+ qubits while maintaining fabrication uniformity; realize transversal operations of logical Clifford gates
Ion Trap: Scale from 56 ions to 100—200 ions (multi-module interconnection), verify the reliability of remote entanglement
Neutral Atoms: Improve two-qubit gate fidelity from 99.5% to 99.9%, achieve first logical qubit storage demonstration

The credibility of this milestone is relatively high (>70%), as it primarily relies on linear scaling of already proven technologies.

Milestone 2: Logical $T$ Gate Error $<10^{-6}$ (2028—2029)

This is the “gateway” to universal fault-tolerant quantum computing. Requirements:

Upgrade magic state distillation from proof-of-principle demonstration to pipeline production
ASIC decoder replaces FPGA, with latency reduced to $<1\,\mu\text{s}$ (superconducting) or $<1\,\text{ms}$ (ion trap)
Control electronics transition from commercial instruments to custom cryogenic ASICs

Ion trap platforms, with their long coherence times and high gate fidelity, are most likely to reach this milestone first. Superconducting platforms need breakthroughs in cryo-CMOS and on-chip magic state factories.

Milestone 3: Early Prototype (2030—2033)

Defined as: capable of continuously running a useful fault-tolerant quantum algorithm (such as Shor’s algorithm factoring 15—21, or 20—30 qubit quantum chemistry simulations) for over a week, with reproducible results.

Requires all prerequisite milestones to be satisfied simultaneously:

1000—2000 physical qubits ( $d=15\text{--}20$ surface code, 10—20 logical qubits)
Complete Clifford+ $T$ logical gate set
Magic state factory yield $>10^6$ /s
Real-time ASIC decoding, latency $<$ error correction cycle
Auto-calibration system, MTBF $>1000$ hours
Cryogenic/control system integration with continuous operation stability

This milestone has relatively high uncertainty (credibility estimate about 40—60%), as it requires multiple independent technology lines to mature and integrate simultaneously.

Milestone 4: Practical Quantum Computing (2035+)

Defined as: capable of breaking RSA-2048, simulating 100+ qubit strongly correlated quantum systems, or solving optimization problems that classical computers cannot solve within a reasonable time.

This requires:

Millions of physical qubits (assuming surface code still; if LDPC codes mature, could drop to hundreds of thousands)
Logical error rate $<10^{-10}$
Magic state yield $>10^9$ /s
Distributed modular architecture with inter-module quantum links

The timeline for this milestone is highly uncertain. It depends on quantum LDPC codes still in their theoretical phase, unverified cryo-CMOS technology, and the possible emergence of entirely new physical platforms. Placing it at “2035+” reflects: even if all known technologies develop along the most optimistic path, it will take at least a decade to reach this level.

Sources of Uncertainty

The uncertainty in the above timeline comes from three fundamental “unknowns”:

The winning physical platform. There is currently no evidence indicating which of superconducting, ion trap, neutral atom, or silicon spin will dominate in the long term. Each platform has unique advantages and critical weaknesses. New physical platforms (such as topological qubits) may emerge in the future, fundamentally changing the timeline.
A paradigm shift in error-correcting codes. If quantum LDPC codes or their variants are proven physically feasible with sufficiently high thresholds, the physical qubit requirement may drop from hundreds of millions to hundreds of thousands, significantly advancing the timeline. Conversely, if LDPC codes cannot be realized, the high overhead of the surface code will severely delay practical quantum computing.
Non-linearity of engineering integration. Breakthroughs in individual technology nodes (such as higher gate fidelity) do not necessarily translate linearly into system performance improvements. New bottlenecks may emerge during integration (such as bus transport errors, inter-module synchronization, and global calibration drift), and these problems only become apparent when approaching the prototype stage.

Closing: The Beginning of an Engineering Roadmap

The seven engineering milestones in this chapter are not the end of prophecy, but the beginning of an engineering roadmap. Each milestone corresponds to specific quantitative metrics, physical limitations, and technical pathways. The expansion from $10^2$ to $10^{3\text{--}4}$ physical qubits, the logical gate set from Clifford to Clifford+ $T$ , the decoder evolution from FPGA to ASIC, the operational stability from hours to weeks — these are not abstract research topics, but yield curves in the foundry, thermal load calculations in the dilution refrigerator, and signal integrity analyses on the PCB.

The ultimate challenge of quantum computing is not to prove the correctness of quantum mechanics (that has long been established), but to embed the mathematical structure of quantum mechanics into an engineering system that is sufficiently reliable, sufficiently fast, and sufficiently large. This system must operate near absolute zero, manipulate individual electrons or atoms with microwaves and lasers, correct continuous errors on nanosecond timescales, and execute billions of operations with over 99.999% precision.

This is not a physics problem. This is an engineering problem — one that may take a decade or longer to solve. But it is precisely at each of these engineering milestones that the journey of quantum computing from theory to reality becomes concrete, measurable, and traceable.

Chapter 6 Summary

This chapter has systematically reviewed, from an engineering perspective, the seven core engineering milestones from the current state of quantum computing to early prototypes:

6.1 Current state of the art — Willow sub-threshold storage error correction, Quantinuum logical gates + magic state distillation, quantum advantage demonstrations (Sycamore 2019 to Willow 2024)
6.2 Qubit scaling — fabrication yield, wiring density, and modularity bottlenecks across superconducting, ion trap, neutral atom, and silicon spin platforms
6.3 Universal fault-tolerant gates — the gap from Clifford to Clifford+ $T$ , the logical $T$ gate has not yet completed a fault-tolerant demonstration
6.4 Industrial magic state distillation — the yield leap from proof-of-principle to millions of $T$ gates per run
6.5 Real-time decoders — from FPGA to ASIC, sub-microsecond latency and high-bandwidth challenges
6.6 Cryogenic/control system integration — bridging the $10^5$ -fold thermal load gap (Cryo-CMOS, HTS interconnects, microwave-over-optical)
6.7 Efficient error-correcting codes and interconnection — the surface code’s $d^2:1$ overhead and quantum LDPC code’s ~10:1 prospect

These seven milestones together constitute the complete development roadmap for quantum computing from “laboratory physics demonstration” to “engineered computing system.” Each milestone has clear quantitative metrics and engineering pathways, but the resolution time for each is filled with uncertainty. The practical realization of quantum computing is not a single breakthrough achieved overnight, but the successive conquest of these engineering milestones.

(End of Chapter 6)

Appendix

Quantum Computing Tutorial Visual Diagram Specifications

Quantum Computing Tutorial — Visual Diagram Specifications

Overview

This document provides detailed visual diagram/illustration specifications for the quantum computing introductory tutorial. Each diagram includes: (a) title, (b) tutorial chapter reference, (c) detailed visual description, (d) recommended tools, (e) key elements and color scheme. All specifications are detailed enough for illustrators or researchers to create high-quality vector graphics directly from them.

Global Color Palette

To maintain visual consistency throughout the tutorial, all diagrams should follow the unified color scheme below:

Color Role	Hex Value	Usage
Primary Quantum Blue	`#2563EB`	Quantum states, Bloch sphere vectors, quantum circuit main lines
Superposition Purple	`#7C3AED`	Superposition states, probability amplitudes, complex plane
Entanglement Red	`#DC2626`	Entangled states, Bell states, correlation measurements
Classical Gray	`#4B5563`	Classical bits, classical circuits, reference frames
Energy Orange	`#F59E0B`	Excited states, energy levels, microwave photons
Ground Teal	`#0D9488`	Ground states, low energy levels, stable states
Interference Green	`#10B981`	Constructive interference, correct solution amplitudes
Decoherence Brown	`#92400E`	Noise, decoherence, errors
Background Light	`#F8FAFC`	Diagram background
Grid Line	`#E2E8F0`	Coordinate grid, guide lines

Note: All diagrams use a uniform background of #F8FAFC with text in #1E293B (deep slate) to ensure readability.

Diagram Specifications

Diagram 1: Complex Plane — Addition (Parallelogram Rule)

Complex Plane — Addition (Parallelogram Rule)

Chapter: Chapter 1 “Quantum Superposition and Exponential State Space” / Section 1.1
Purpose: Visually demonstrate the geometric meaning of complex number addition on the complex plane, laying the groundwork for understanding the mathematical basis of quantum state superposition.
Recommended Tools: TikZ (LaTeX), Matplotlib (Python)
Detailed Description:
1. Coordinate System: Draw a standard 2D Cartesian coordinate system with the horizontal axis as the real part (Re) and the vertical axis as the imaginary part (Im). Label Re and Im at the ends of the axes. Use light gray grid (#E2E8F0), line width 0.5 pt.
2. Complex Vectors: Draw three directed segments (arrows) from the origin:
  - Vector $z_1 = 2 + i$ : Draw in Quantum Blue (#2563EB), label the arrow tip " $z_1 = 2 + i$ "
  - Vector $z_2 = 1 + 3i$ : Draw in Superposition Purple (#7C3AED), label the arrow tip " $z_2 = 1 + 3i$ "
  - Resultant vector $z_1 + z_2 = 3 + 4i$ : Draw in Entanglement Red (#DC2626), with thicker line width (2 pt), label the arrow tip " $z_1 + z_2 = 3 + 4i$ "
3. Parallelogram Construction:
  - From the tip of $z_1$ , draw a dashed line parallel and equal in length to $z_2$ (dashed, line width 1 pt, color #7C3AED, 50% opacity)
  - From the tip of $z_2$ , draw a dashed line parallel and equal in length to $z_1$ (dashed, line width 1 pt, color #2563EB, 50% opacity)
  - The two dashed lines should meet at the tip of the resultant vector, forming a complete parallelogram
4. Angle Labels: Label angle $\theta_1$ between $z_1$ and the real axis, and angle $\theta_2$ between $z_2$ and the real axis, using small arc lines, arc color #4B5563
5. Text Explanation: Add a text box at the bottom right of the diagram with the content: “Geometric meaning of complex addition: the parallelogram rule. The superposition of quantum states $|\psi\rangle = \alpha|0\rangle + \beta|1\rangle$ is mathematically a linear combination of complex vectors.”
Size Suggestion: Width 12 cm x Height 10 cm
Font: Sans-serif (such as Source Sans Pro or Noto Sans), axis labels 10 pt, complex number labels 9 pt

ASCII Placeholder:

      Im
       |
    4  +...........* z1+z2
       |         / |
    3  +    z2  /  |
       |    *  /   |
    2  +   /\ /    |
       |  /  * z1  |
    1  + /         |
       |/          |
    ---+---+---+---+--- Re
       0   1   2   3
       |
    [Complex addition = Parallelogram rule]

Diagram 2: Complex Plane — Multiplication (Rotation + Scaling)

Complex Plane — Multiplication (Rotation + Scaling)

Chapter: Chapter 1 “Quantum Superposition and Exponential State Space” / Section 1.1
Purpose: Show the geometric effect of complex multiplication — magnitudes multiply, arguments add. This is the mathematical basis for understanding quantum gate operations such as phase gates $S$ and $T$ .
Recommended Tools: TikZ (LaTeX), Matplotlib (Python)
Detailed Description:
1. Coordinate System: Same as Diagram 1 — standard complex plane with Re/Im labels and light gray grid.
2. Original Vector: Draw a vector $z = 1 + i$ from the origin (i.e., $\sqrt{2}e^{i\pi/4}$ ), using Quantum Blue (#2563EB), line width 1.5 pt, label the tip " $z = 1 + i$ "
3. Multiplier: Draw the unit circle as a dashed line (line width 0.8 pt, color #4B5563, 40% opacity). Mark the position of the multiplier $w = e^{i\pi/3}$ on the unit circle using a small dot (radius 3 pt, color #F59E0B), with " $w = e^{i\pi/3}$ " labeled next to it.
4. Resultant Vector: Draw the product $z \cdot w = \sqrt{2}e^{i7\pi/12}$ , using Interference Green (#10B981), line width 2 pt, label the tip ” $z \cdot w$ (rotated by $\pi/3$ )”
5. Rotation Arc: Draw a large arc from $z$ to $z \cdot w$ , labeling the rotation angle " $+\pi/3$ ", arc color #F59E0B, line width 1.2 pt
6. Magnitude Comparison: Use thin dashed lines (#E2E8F0) to project from the three vector tips to the real axis, showing that $z$ and $z \cdot w$ have equal magnitudes (because $|w|=1$ ), and draw only a reference scaling arrow from the tip of $z$ toward the unit circle
7. Text Explanation: Bottom-right text box content: “Multiplying by the unit complex number $e^{i\phi}$ is equivalent to rotating the vector by angle $\phi$ . The magnitude remains unchanged; only the phase changes. This is precisely the mathematical essence of the quantum phase gates $S$ and $T$ .”
Size Suggestion: Width 12 cm x Height 12 cm
Font: Same as Diagram 1

ASCII Placeholder:

      Im
       |
    2  +      * z·w
       |     /
    1  +    * z        * w=e^{iπ/3}
       |   /           /
    ---+--+---+---+---+--- Re
       0  1   2   3
       |
    [Complex multiplication = Rotation + Scaling]
    z·w = |z||w| · e^{i(θz+θw)}

Diagram 3: Classical Bit vs Qubit — State Space Comparison

Classical Bit vs Qubit — State Space Comparison

Chapter: Chapter 2 “Essential Differences Between Quantum and Classical Computing” / Section 2.1
Purpose: Use geometric figures to contrast the discrete states of a classical bit with the continuous state space of a qubit (points on the Bloch sphere).
Recommended Tools: TikZ (LaTeX), Adobe Illustrator
Detailed Description:
1. Layout: Left-right split layout, with “Classical Bit” on the left and “Qubit” on the right, separated by a thin vertical line (#E2E8F0, line width 1 pt).
2. Left Side — Classical Bit:
  - Title: “Classical Bit,” bold font, color #4B5563
  - Draw two solid dots: “0” at the top (fill #0D9488, radius 8 pt) and “1” at the bottom (fill #F59E0B, radius 8 pt), connected by a vertical line segment
  - Label next to the line: “State space: $\{0, 1\}$ (two discrete points)”
  - Add explanatory text to the right of the dots: “Deterministic state: every reading yields a definite value”
3. Right Side — Qubit:
  - Title: “Qubit,” bold font, color #2563EB
  - Draw a 2D cross-section of the Bloch sphere (a circle), circumference in #2563EB (line width 2 pt)
  - Inside the circle, draw a vector arrow from the center pointing approximately 45 degrees to the upper right, color #7C3AED, line width 2 pt, label the tip " $|\psi\rangle = \alpha|0\rangle + \beta|1\rangle$ "
  - Label " $|0\rangle$ " at the top of the circle (north pole, #0D9488) and " $|1\rangle$ " at the bottom (south pole, #F59E0B)
  - Label next to the vector arrow: " $|\alpha|^2 + |\beta|^2 = 1$ "
  - Add explanatory text to the right of the circle: “Continuous state space: any point on the sphere, superposition states can contain both 0 and 1”
4. Bottom Summary: A summary text box spanning both columns with the content: ” $n$ classical bits: one of $2^n$ states; $n$ qubits: one unit vector in a $2^n$ -dimensional Hilbert space.”
Size Suggestion: Width 16 cm x Height 8 cm
Font: Title 12 pt, body text 9 pt

ASCII Placeholder:

  [Classical Bit]              [Qubit]
     0                      |0⟩ (North Pole)
     |                        \
     |                         \ |ψ⟩
     1                        /
                          |1⟩ (South Pole)
  {0,1} Two discrete points         Any point on sphere

Diagram 4: Bloch Sphere — 3D Wireframe Overview

Bloch Sphere — 3D Wireframe Overview

Chapter: Chapter 2 “Physical Implementation and Characterization of Qubits” / Throughout tutorial
Purpose: Provide a standard 3D view of the Bloch sphere with all key quantum states labeled, as a geometric reference for understanding single-qubit gate operations.
Recommended Tools: TikZ (3D library such as tikz-3dplot), Asymptote, Python (Matplotlib mplot3d), Blender (render then export vector graphics)
Detailed Description:
1. Sphere: Draw a 3D wireframe sphere, with the equatorial plane and two meridians (x-z plane and y-z plane) shown as solid lines and the remaining latitude/longitude lines as dashed lines. Sphere outline line width 1.5 pt, color #1E293B. Dashed line opacity 30%.
2. Axes: Draw three coordinate axes x, y, z extending outward from the sphere center, about 20% beyond the sphere surface. Label axis ends: $x$ (right), $y$ (left-back), $z$ (up). Axis color #4B5563, line width 1 pt.
3. Key Quantum State Labels (using leader lines with small dots):
  - $|0\rangle$ ：North Pole (positive z direction), dot color #0D9488 (Ground Teal), diameter 6 pt, labeled " $|0\rangle$ "
  - $|1\rangle$ ：South Pole (negative z direction), dot color #F59E0B (Energy Orange), diameter 6 pt, labeled " $|1\rangle$ "
  - $|+\rangle = \frac{1}{\sqrt{2}}(|0\rangle + |1\rangle)$ ：Positive x direction (front of equator), dot color #2563EB (Quantum Blue), diameter 6 pt, labeled " $|+\rangle$ "
  - $|-\rangle = \frac{1}{\sqrt{2}}(|0\rangle - |1\rangle)$ ：Negative x direction (back of equator), dot color #7C3AED (Superposition Purple), diameter 6 pt, labeled " $|-\rangle$ "
  - $|+i\rangle = \frac{1}{\sqrt{2}}(|0\rangle + i|1\rangle)$ ：Positive y direction (right of equator), dot color #10B981 (Interference Green), diameter 6 pt, labeled " $|+i\rangle$ "
  - $|-i\rangle = \frac{1}{\sqrt{2}}(|0\rangle - i|1\rangle)$ ：Negative y direction (left of equator), dot color #DC2626 (Entanglement Red), diameter 6 pt, labeled " $|-i\rangle$ "
4. Example State Vector: Draw a thick vector arrow from the sphere center to $|+\rangle$ (line width 2.5 pt, color #2563EB), and label beside the middle of the arrow: " $|\psi\rangle = \cos\frac{\theta}{2}|0\rangle + e^{i\phi}\sin\frac{\theta}{2}|1\rangle$ "
5. Angle Labels:
  - Label polar angle $\theta$ with a small arc between the z-axis and the state vector
  - On the equatorial plane, label azimuthal angle $\phi$ with an arc from the x-axis to the projection of the state vector
  - Arc color #4B5563, line width 0.8 pt
6. Viewpoint: Use an isometric view with a slight downward angle (elevation ~20 degrees), so the z-axis points up, the x-axis points lower-right, and the y-axis points lower-left.
7. Legend: Add a small legend in the bottom-right corner explaining the state category corresponding to each dot color (ground/excited/superposition).
Size Suggestion: Width 14 cm x Height 14 cm
Font: Quantum state labels 11 pt (bold), angle labels 9 pt, formulas 10 pt

ASCII Placeholder:

              z
              |  |0⟩
              | /
              |/
    |−i⟩ -----+----- |+i⟩
             /|\
            / | \
           /  |  \
              |1⟩
           [Bloch Sphere]

Diagram 5: Bloch Sphere — Single-Qubit Gate Operations

Bloch Sphere — Single-Qubit Gate Operations

Chapter: Chapter 3 “Quantum Gate Operations” / Section 3.1
Purpose: Visualize the geometric action of $X$ , $Y$ , $Z$ , $H$ , $S$ , $T$ gates on the Bloch sphere.
Recommended Tools: TikZ (3D library), Asymptote, Python (Matplotlib mplot3d)
Detailed Description:
1. Layout: Arrange in a 2x3 subplot grid, each subplot showing one gate operation, with 1 cm spacing between subplots.
2. Common Elements in Each Subplot:
  - Small Bloch sphere wireframe (about 3.5 cm diameter)
  - North pole $|0\rangle$ (#0D9488) and south pole $|1\rangle$ (#F59E0B) labels
  - Initial state vector (thin dashed arrow, color #94A3B8, line width 1 pt)
  - Final state vector (thick solid arrow, color #2563EB, line width 2 pt)
  - Rotation arc (arc beside the arrow indicating rotation axis and direction, color #F59E0B, line width 1.2 pt)
3. Detailed Gate Operations:
  - $X$ gate (NOT / Pauli-X): Subplot title ” $X$ $X$ gate: rotation by $\pi$ $π$ around the $x$ $x$ axis”
    - Initial state: $|0\rangle$ (north pole, dashed)
    - Final state: $|1\rangle$ (south pole, solid)
    - Rotation arc: along a meridian from north pole to south pole, labeled “rotation by $\pi$ around $x$ axis”
  - $Y$ gate (Pauli-Y): Subplot title ” $Y$ $Y$ gate: rotation by $\pi$ $π$ around the $y$ $y$ axis”
    - Initial state: $|0\rangle$
    - Final state: $|1\rangle$ (but path differs from $X$ gate, along a y-z plane meridian)
    - Rotation arc labeled “rotation by $\pi$ around $y$ axis”
  - $Z$ gate (Pauli-Z / Phase Flip): Subplot title ” $Z$ $Z$ gate: rotation by $\pi$ $π$ around the $z$ $z$ axis”
    - Initial state: $|+\rangle$ (positive x direction)
    - Final state: $|-\rangle$ (negative x direction)
    - Rotation arc: along the equator from $|+\rangle$ to $|-\rangle$ , labeled “rotation by $\pi$ around $z$ axis”
  - $H$ gate (Hadamard): Subplot title ” $H$ $H$ gate: Hadamard transform”
    - Initial state: $|0\rangle$ (north pole)
    - Final state: $|+\rangle$ (equator, positive x direction)
    - Use dashed lines to show equivalent paths: $|0\rangle \to |+\rangle$ and $|1\rangle \to |-\rangle$
    - Add a small note: " $H = \frac{1}{\sqrt{2}}\begin{pmatrix}1 & 1 \\ 1 & -1\end{pmatrix}$ "
  - $S$ gate (Phase gate): Subplot title ” $S$ $S$ gate: rotation by $\pi/2$ $π /2$ around the $z$ $z$ axis”
    - Initial state: $|+\rangle$
    - Final state: $|+i\rangle$ (positive y direction)
    - Rotation arc: along the equator by 90 degrees, labeled " $\pi/2$ "
  - $T$ gate ( $\pi/8$ gate): Subplot title ” $T$ $T$ gate: rotation by $\pi/4$ $π /4$ around the $z$ $z$ axis”
    - Initial state: $|+\rangle$
    - Final state: located 22.5 degrees above the equator (marked with a small dot, no standard name)
    - Rotation arc: along the equator by 45 degrees, labeled " $\pi/4$ "
    - Add a note: " $T = \begin{pmatrix}1 & 0 \\ 0 & e^{i\pi/4}\end{pmatrix}$ "
4. Overall Title: Centered title at the top of the diagram: “Single-Qubit Gates on the Bloch Sphere,” font 14 pt, bold, color #1E293B.
Size Suggestion: Width 18 cm x Height 12 cm
Font: Subplot titles 10 pt, formulas 8 pt, labels 8 pt

ASCII Placeholder:

  [X]      [Y]      [Z]      [H]      [S]      [T]
   |0⟩        |0⟩       |+⟩→|−⟩    |0⟩→|+⟩   |+⟩→|+i⟩   |+⟩→·
   ↓          ↓          ○         ↘         ○          ○
   |1⟩        |1⟩                  |+⟩                 (π/4)
  (around x π)   (around y π)    (around z π)

Diagram 6: Double-Slit Experiment — Schematic Diagram

Double-Slit Experiment — Schematic Diagram

Chapter: Chapter 1 “Quantum Interference” / Section 1.3
Purpose: Use the classic double-slit experiment schematic to explain the physical origin of quantum interference, connecting wave-particle duality with amplitude interference in quantum computing.
Recommended Tools: TikZ (LaTeX), Adobe Illustrator、Inkscape
Detailed Description:
1. Overall Layout: From left to right: “Light Source -> Double Slit -> Interference Screen,” in a side-view cross-section style.
2. Light Source (far left):
  - Draw a simplified single-photon source: a cylindrical container (representing a laser or single-photon source), labeled “Single-Photon Source” on the left
  - Emit three parallel thin straight lines from the source to the right representing photon paths, color #2563EB, line width 0.8 pt
3. Double Slit (middle):
  - Draw a vertical barrier, about 6 cm high, color #1E293B, line width 2 pt
  - Cut two vertical slits in the barrier of equal width (about 0.5 cm), slit separation about 2 cm
  - Label the barrier on the left: “Double Slit”
4. Wavefront Propagation (right of barrier):
  - Draw semi-circular wavefronts propagating to the right from each slit, using concentric semi-circular arcs
  - Upper slit wavefronts: color #2563EB, line width 0.6 pt, opacity decreasing from 80% to 30%
  - Lower slit wavefronts: color #7C3AED, line width 0.6 pt, opacity decreasing from 80% to 30%
  - At the intersections of the two wavefront trains, highlight “Constructive Interference” in Interference Green (#10B981) and “Destructive Interference” in Decoherence Brown (#92400E)
5. Interference Screen (far right):
  - Draw a vertical detection screen, color #1E293B, line width 1.5 pt
  - Draw an interference fringe pattern on the screen: a series of vertical bright and dark stripes
  - Bright stripes: fill #10B981, height proportional to intensity (highest in the center, decreasing toward the sides)
  - Dark stripes: fill #F8FAFC (same as background, creating a recessed appearance)
  - Overlay a smooth intensity envelope curve to the right of the screen, drawn in #DC2626, labeled “Intensity $I(x)$ ”
6. Labels and Notes:
  - Add the formula in the wavefront region: " $|\psi_{\text{total}}|^2 = |\psi_1 + \psi_2|^2 = |\psi_1|^2 + |\psi_2|^2 + 2|\psi_1||\psi_2|\cos\delta$ "
  - Add a note at the bottom of the diagram: “When a single photon passes through both slits simultaneously, its probability amplitudes interfere, forming alternating bright and dark fringes. This is one of the physical foundations of quantum computing.”
7. Color Emphasis: Use bright colors (#10B981) for constructive interference regions and dark colors (#92400E at 30% opacity) for destructive interference regions, creating a strong contrast.
Size Suggestion: Width 18 cm x Height 10 cm
Font: Labels 9 pt, formulas 10 pt, notes 9 pt

ASCII Placeholder:

  [Single Photon Source]  →→→   ||    ～～～～～～～    |▓|▓|▓|▓|▓|  [Detection Screen]
                     ||   ~ Constructive ~~~     | | | | | |   [Intensity curve]
                    Double Slit   ~~ Destructive ~~      Interference fringes
                         [Probability amplitude interference]

Diagram 7: Quantum Measurement and Wavefunction Collapse

Quantum Measurement and Wavefunction Collapse

Chapter: Chapter 2 “Measurement” / Section 2.3
Purpose: Visualize the wavefunction collapse process caused by quantum measurement, showing how a superposition state irreversibly collapses to an eigenstate.
Recommended Tools: TikZ (LaTeX, using tikzducks or custom figures), Adobe Illustrator
Detailed Description:
1. Layout: Use a timeline layout showing four stages from left to right: “Preparation -> Evolution -> Measurement -> Collapse,” each stage about 4 cm wide.
2. Stage 1: State Preparation
  - Title: “Preparation”
  - Draw a small Bloch sphere outline (only the upper half visible), with a small dot at the center representing the qubit
  - Label " $|0\rangle$ " (#0D9488)
  - Note below: “Initialize to ground state”
3. Stage 2: Unitary Evolution
  - Title: “Evolution”
  - Draw a complete Bloch sphere, with a point on the surface 45 degrees above the equator, using a vector arrow to represent the superposition state
  - Label " $|\psi\rangle = \frac{1}{\sqrt{2}}(|0\rangle + |1\rangle)$ "
  - Vector color #7C3AED (Superposition Purple)
  - Note below: “Apply Hadamard gate, enter superposition state”
4. Stage 3: Measurement
  - Title: “Measurement”
  - Draw a simplified measurement apparatus icon: a box with a pointer gauge on top
  - Draw a projection symbol inside the box (e.g., $\Pi_0 = |0\rangle\langle 0|$ )
  - Draw a dashed arrow from the superposition state on the left pointing to the measurement apparatus, color #2563EB
  - Note below: “Projective measurement $M = \sum_m m P_m$ ”
5. Stage 4: Collapse
  - Title: “Collapse”
  - Draw two parallel possible outcomes, represented by branching arrows:
    - Upper branch (50% probability): pointing to " $|0\rangle$ " (#0D9488), labeled " $P(|0\rangle) = |\alpha|^2 = 0.5$ "
    - Lower branch (50% probability): pointing to " $|1\rangle$ " (#F59E0B), labeled " $P(|1\rangle) = |\beta|^2 = 0.5$ "
  - Branching arrows originate from the measurement apparatus, using different colors (upper #0D9488, lower #F59E0B)
  - Between the two outcomes, draw a diagonal line through the superposition state vector diagram, indicating the superposition is destroyed
  - Note below: “Irreversible collapse to eigenstate, superposition information lost”
6. Timeline: Draw a horizontal timeline below the four stages, labeled ” $t_0$ , $t_1$ , $t_2$ , $t_3$ ,” axis color #4B5563
7. Warning Box: Add a prominent warning box at the bottom of the diagram (border #DC2626, background #FEF2F2), with the content: “Note: Measurement is the most fundamental bottleneck in quantum computing. Although the computation process can exploit an exponentially large state space, measurement can only extract classical information (Holevo bound).”
Size Suggestion: Width 18 cm x Height 10 cm
Font: Stage titles 11 pt (bold), notes 9 pt, formulas 10 pt

ASCII Placeholder:

  [Preparation]     [Evolution]         [Measurement]        [Collapse]
    |0⟩  →  |ψ⟩=(|0⟩+|1⟩)/√2  →  [[gauge]]  →  |0⟩ (50%)
                                      ↘
                                        |1⟩ (50%)
  "Measurement causes irreversible wavefunction collapse"

Diagram 8: Quantum Circuit — Bell State Preparation

Quantum Circuit — Bell State Preparation

Chapter: Chapter 2 “Generation of Quantum Entanglement” / Section 2.1, and Chapter 3 “Quantum Gate Operations” / Section 3.1
Purpose: Show the quantum circuit diagram for the standard Bell state $|\Phi^+\rangle = \frac{1}{\sqrt{2}}(|00\rangle + |11\rangle)$ .
Recommended Tools: QuTiP (Python), Qiskit (circuit_drawer), TikZ (quantikz package)
Detailed Description:
1. Circuit Structure: Standard quantum circuit diagram with two horizontal wires (qubit lines), with gate operations arranged from left to right.
2. Qubit Lines:
  - Upper line: labeled " $q_0$ " (left side), color #1E293B
  - Lower line: labeled " $q_1$ " (left side), color #1E293B
  - Two horizontal lines using #1E293B, line width 1.5 pt, length about 10 cm
3. Gate Operations (left to right):
  - $H$ gate: Located on the $q_0$ line, 2 cm from the left end. Draw a square box, side 0.8 cm, border #2563EB (line width 1.5 pt), labeled " $H$ " inside (font 12 pt, color #1E293B). Fill #EFF6FF (very light quantum blue) inside the box.
  - CNOT gate: Located 2 cm to the right of the $H$ $H$ gate.
    - Control: Draw a solid dot on the $q_0$ line, diameter 0.5 cm, color #2563EB
    - Target: Draw a circle with a ”+” sign on the $q_1$ line (⊕), outer circle diameter 0.8 cm, line width 1.5 pt, color #DC2626; inner ”+” line width 1.2 pt, color #DC2626
    - Connect control and target with a vertical solid line, color #1E293B, line width 1.5 pt
4. Input State Labels:
  - At the far left of the circuit, label the $q_0$ line " $|0\rangle$ " (#0D9488)
  - Label the $q_1$ line " $|0\rangle$ " (#0D9488)
5. Output State Labels:
  - At the far right, connect the two lines with a large curly brace, labeling " $|\Phi^+\rangle = \frac{1}{\sqrt{2}}(|00\rangle + |11\rangle)$ "
  - Label color #DC2626 (Entanglement Red), font 11 pt
6. State Evolution Labels (below the circuit):
  - Below the $H$ gate: " $|00\rangle \xrightarrow{H} \frac{1}{\sqrt{2}}(|00\rangle + |10\rangle)$ "
  - Below the CNOT gate: " $\xrightarrow{\text{CNOT}} \frac{1}{\sqrt{2}}(|00\rangle + |11\rangle) = |\Phi^+\rangle$ "
7. Auxiliary Note: Add a small note box at the bottom right: “The $H$ gate prepares $q_0$ into a superposition state; the CNOT gate uses $q_0$ as the control to transfer the superposition phase information to $q_1$ , thereby generating entanglement.”
Size Suggestion: Width 16 cm x Height 8 cm
Font: Gate labels 12 pt, qubit labels 10 pt, state labels 10 pt, evolution formulas 9 pt

ASCII Placeholder:

  q0: |0⟩ ───[H]───●─── |Φ⁺⟩ = (|00⟩+|11⟩)/√2
                   │
  q1: |0⟩ ─────────⊕───
  
  Step 1: H → (|00⟩+|10⟩)/√2
  Step 2: CNOT → (|00⟩+|11⟩)/√2

Diagram 9: Quantum Circuit — Quantum Teleportation

Quantum Circuit — Quantum Teleportation

Chapter: Quantum communication topic (if applicable) or as an extended example of entanglement applications
Purpose: Show the complete circuit for quantum teleportation, one of the most direct applications of quantum entanglement.
Recommended Tools: Qiskit (circuit_drawer), TikZ (quantikz), QuTiP
Detailed Description:
1. Circuit Structure: Three horizontal wires representing:
  - $q_0$ : Unknown qubit $|\psi\rangle$ that Alice wants to teleport
  - $q_1$ : Half of the Bell state held by Alice
  - $q_2$ : Other half of the Bell state held by Bob
2. Input State Labels (left):
  - $q_0$ : " $|\psi\rangle = \alpha|0\rangle + \beta|1\rangle$ " (#7C3AED)
  - $q_1$ : " $|0\rangle$ " (#0D9488)
  - $q_2$ : " $|0\rangle$ " (#0D9488)
3. Gate Operations (left to right):
  - Bell State Preparation Region ( $q_1$ - $q_2$ ):
    - $H$ gate on $q_1$ (same style as Diagram 8)
    - CNOT gate ( $q_1$ control, $q_2$ target)
    - Add a dashed box above this region, labeled “EPR Pair Preparation,” box color #E2E8F0
  - Alice’s Operation Region ( $q_0$ - $q_1$ ):
    - CNOT gate ( $q_0$ control, $q_1$ target)
    - $H$ gate on $q_0$
    - Add a dashed box above this region, labeled “Alice’s Operations”
  - Measurement ( $q_0$ , $q_1$ ):
    - Draw measurement symbols at the far right of $q_0$ and $q_1$ : a semi-circular gauge (similar to Diagram 7), labeled " $M$ " inside
    - Measurement symbol color #4B5563
    - Extend double lines to the right from the measurement symbols (representing classical bits), labeled " $c_0$ " and " $c_1$ "
  - Bob’s Correction ( $q_2$ ):
    - Connect classical bit line $c_1$ to the right to a controlled- $Z$ gate on $q_2$ (hollow dot control, $Z$ box target)
    - Connect classical bit line $c_0$ to the right to a controlled- $X$ gate on $q_2$ (hollow dot control, $\oplus$ target)
    - Classical control lines use dashed lines (#4B5563, line width 1 pt, dash pattern: 3pt 2pt)
    - Label above Bob’s operation region: “Classical-Controlled Correction”
4. Output: Label the far right of $q_2$ as " $|\psi\rangle$ " (#7C3AED), indicating the unknown state has been successfully transmitted to Bob
5. Key Notes: Add process notes below the circuit:
  - Step 1: Prepare EPR pair " $|\Phi^+\rangle_{12}$ "
  - Step 2: Alice performs Bell measurement
  - Step 3: Alice sends 2-bit result through classical channel
  - Step 4: Bob applies $X$ and/or $Z$ gates based on the result to recover $|\psi\rangle$
6. Emphasis: Add a note at the bottom in #DC2626: “Note: Quantum teleportation transmits quantum state information, not matter itself. The entire process does not violate relativity (classical communication speed <= c).”
Size Suggestion: Width 20 cm x Height 12 cm
Font: Qubit labels 10 pt, gate labels 11 pt, notes 9 pt

ASCII Placeholder:

  q0: |ψ⟩ ───●───[H]─M─c0────────────────
              │        ║                  
  q1: |0⟩ ───[H]───●───M─c1────────────────
                   │      ║                
  q2: |0⟩ ─────────⊕──────┼───[Z]c1──[X]c0── |ψ⟩
                          └───Classical communication──┘
  
  [Quantum teleportation: entanglement + classical communication = state transfer]

Diagram 10: Quantum Circuit — GHZ State Preparation

Quantum Circuit — GHZ State Preparation

Chapter: Chapter 2 “Quantum Entanglement” / Multi-partite entanglement extension
Purpose: Show the preparation circuit for the Greenberger-Horne-Zeilinger (GHZ) state, an example of multi-partite entanglement beyond Bell states.
Recommended Tools: Qiskit, TikZ (quantikz)
Detailed Description:
1. Circuit Structure: Three horizontal wires ( $q_0$ , $q_1$ , $q_2$ ), scalable representation.
2. Input State: All three qubits initialized to " $|0\rangle$ " (#0D9488)
3. Gate Operations:
  - $H$ gate on $q_0$ (same style as Diagram 8)
  - CNOT gate 1: $q_0$ control, $q_1$ target
  - CNOT gate 2: $q_1$ control, $q_2$ target (or $q_0$ control $q_2$ , both equivalent)
  - Spacing between the two CNOT gates about 2.5 cm
4. Output State: Label the right side of the three wires with a curly brace: " $|\text{GHZ}\rangle = \frac{1}{\sqrt{2}}(|000\rangle + |111\rangle)$ ", color #DC2626
5. State Evolution (below circuit):
  - " $|000\rangle \xrightarrow{H} \frac{1}{\sqrt{2}}(|000\rangle + |100\rangle) \xrightarrow{\text{CNOT}_{01}} \frac{1}{\sqrt{2}}(|000\rangle + |110\rangle) \xrightarrow{\text{CNOT}_{12}} \frac{1}{\sqrt{2}}(|000\rangle + |111\rangle)$ "
6. Extension Note: Add a note below the diagram: “GHZ states can be generalized to $n$ qubits: $|\text{GHZ}_n\rangle = \frac{1}{\sqrt{2}}(|0\rangle^{\otimes n} + |1\rangle^{\otimes n})$ . They are a core resource for quantum cryptography and quantum error correction.”
Size Suggestion: Width 16 cm x Height 8 cm
Font: Same as Diagram 8

ASCII Placeholder:

  q0: |0⟩ ───[H]───●─────── |GHZ⟩ = (|000⟩+|111⟩)/√2
                   │
  q1: |0⟩ ─────────⊕───●───
                      │
  q2: |0⟩ ────────────⊕───

Diagram 11: Entanglement Correlation — Bell State Measurement Table

Entanglement Correlation — Bell State Measurement Table

Chapter: Chapter 1 “Quantum Entanglement” / Section 1.2, and Chapter 2 “Generation of Quantum Entanglement” / Section 2.2
Purpose: Use a table and schematic diagram to show the measurement correlation properties of the four Bell states, visually presenting the non-classical correlations of quantum entanglement.
Recommended Tools: LaTeX (booktabs + tikz), Adobe Illustrator, Microsoft Excel (export vector graphics)

Detailed Description:

Layout: Two parts. Top: “Correlation Table”; Bottom: “Measurement Schematic.”

Correlation Table:

Table title: “Measurement Correlations of Bell States”

5 columns 5 rows:

Bell State	$q_0$ basis	$q_1$ basis	Joint outcome	Correlation type
$	\Phi^+\rangle = \frac{	00\rangle+	11\rangle}{\sqrt{2}}$	$Z$ basis
$	\Phi^-\rangle = \frac{	00\rangle-	11\rangle}{\sqrt{2}}$	$Z$ basis
$	\Psi^+\rangle = \frac{	01\rangle+	10\rangle}{\sqrt{2}}$	$Z$ basis
$	\Psi^-\rangle = \frac{	01\rangle-	10\rangle}{\sqrt{2}}$	$Z$ basis

Table style:
- Header background #2563EB, white bold text
- Alternating row backgrounds #F8FAFC and #EFF6FF
- Border using #E2E8F0, line width 0.5 pt
- “Perfect positive” cell text color #10B981, bold
- “Perfect anti-correlation” cell text color #DC2626, bold

Measurement Schematic (below table):
- Draw two separated measurement apparatus icons (same gauge style as Diagram 7), labeled “Alice” and “Bob,” spaced about 6 cm apart
- Draw a wavy line between the two apparatuses (using a sine wave or tilde shape), color #DC2626, line width 1.5 pt, labeled “Quantum Entanglement”
- Alice’s gauge shows “0,” Bob’s gauge also shows “0” (representing one measurement outcome of $|\Phi^+\rangle$ )
- Add a curly brace below both, labeled: “Measurement results are always identical (perfect correlation), even when separated by light-years. Einstein called this ‘spooky action at a distance.’”
CHSH Note: Add at the very bottom in small font: “This correlation cannot be explained by any classical local hidden variable theory (Bell inequality violation).”

Size Suggestion: Width 18 cm x Height 14 cm
Font: Header 10 pt, data 9 pt, notes 9 pt

ASCII Placeholder:

  ┌──────────┬─────────┬─────────┬──────────┬──────────┐
  │ Bell State │ q0 basis │ q1 basis │ Outcome  │ Correlation │
  ├──────────┼─────────┼─────────┼──────────┼──────────┤
  │ |Φ⁺⟩     │ Z       │ Z       │ 00/11    │ Perfect +   │
  │ |Φ⁻⟩     │ Z       │ Z       │ 00/11    │ Perfect +   │
  │ |Ψ⁺⟩     │ Z       │ Z       │ 01/10    │ Perfect -   │
  │ |Ψ⁻⟩     │ Z       │ Z       │ 01/10    │ Perfect -   │
  └──────────┴─────────┴─────────┴──────────┴──────────┘
  
    [Alice M=0] ~~~~ [Bob M=0]
         " spooky action at a distance "

Diagram 12: Quantum Fourier Transform (QFT) Circuit — n=3 Case

Quantum Fourier Transform Circuit — n=3 Case

Chapter: Chapter 3 “Quantum Phase Estimation and Quantum Fourier Transform” / Section 3.3
Purpose: Show the standard QFT circuit for $n=3$ qubits, the core subroutine of Shor’s algorithm and QPE.
Recommended Tools: Qiskit (circuit_drawer), TikZ (quantikz)
Detailed Description:
1. Circuit Structure: Three horizontal wires ( $q_0$ , $q_1$ , $q_2$ , top to bottom), arranged from most significant to least significant.
2. Input State Label: Label the left side " $|j_1 j_2 j_3\rangle$ ", representing the computational basis state of the 3-bit binary number $j$ .
3. Gate Operations (left to right):
  - $q_2$ (least significant bit) operations:
    - $H$ gate (#2563EB, same style as before)
    - Controlled- $R_2$ gate: control $q_1$ , target $q_2$ . Symbol: solid dot control (#7C3AED), target box labeled " $R_2$ " (#7C3AED)
    - Controlled- $R_3$ gate: control $q_0$ , target $q_2$ . Symbol: solid dot control (#10B981), target box labeled " $R_3$ " (#10B981)
  - $q_1$ operations:
    - $H$ gate
    - Controlled- $R_2$ gate: control $q_0$ , target $q_1$
  - $q_0$ (most significant bit) operations:
    - $H$ gate
  - Swap gate: At the far right of the circuit, swap $q_0$ $q_{0}$ and $q_2$ $q_{2}$ (because QFT output is bit-reversed)
    - Draw crossed “times” symbols between the two lines, labeled “Swap”
4. Gate Color Coding:
  - $H$ gate: border #2563EB, fill #EFF6FF
  - $R_k$ gate ( $R_k = \begin{pmatrix}1 & 0 \\ 0 & e^{2\pi i/2^k}\end{pmatrix}$ ): border color varies with $k$ — $R_2$ uses #7C3AED, $R_3` uses `#10B981`,$ R_4$ uses #F59E0B (if extended)
5. Output State Label: Label the right side: " $\frac{1}{\sqrt{8}}\sum_{k=0}^{7} e^{2\pi i jk/8}|k\rangle$ "
6. Formula Notes (below circuit):
  - ” $R_k = \begin{pmatrix}1 & 0 \\ 0 & e^{2\pi i/2^k}\end{pmatrix}$ , $H = \frac{1}{\sqrt{2}}\begin{pmatrix}1 & 1 \\ 1 & -1\end{pmatrix}$ ”
  - “QFT maps the computational basis state $|j\rangle$ to an equal-weight superposition, with each basis state’s phase being $e^{2\pi i jk/N}$ ”
  - “Total gate count: $O(n^2) = O((\log N)^2)$ , an exponential speedup compared to the classical FFT’s $O(N \log N)$ ”
7. Scalability Note: Add a dashed box at the bottom right: “Scalable Pattern: For each additional qubit, add one wire and apply an $H$ gate and $n-1$ controlled rotation gates.”
Size Suggestion: Width 18 cm x Height 10 cm
Font: Qubit labels 10 pt, gate labels 10 pt, formulas 9 pt

ASCII Placeholder:

  q0: |j1⟩ ───[H]───────────×───
                            │
  q1: |j2⟩ ───●───[H]───────×───
              │      │
  q2: |j3⟩ ───●──────●───[H]───
             R3     R2
  
  [QFT for n=3: O(n²) gates, exponential speedup over FFT]

Diagram 13: Superconducting Qubit — Transmon Simplified Schematic

Superconducting Qubit — Transmon Simplified Schematic

Chapter: Chapter 2 “Physical Implementation of Qubits” / Section 1.2
Purpose: Show the simplified physical structure and energy level diagram of the transmon superconducting qubit, helping to understand its operating principle.
Recommended Tools: TikZ (LaTeX), Adobe Illustrator、Inkscape
Detailed Description:
1. Layout: Left-right split. Left: “Circuit Diagram”; Right: “Energy Level Diagram.”
2. Left Side — Circuit Diagram:
  - Draw a simplified variant of an LC oscillator circuit:
    - A large parallel capacitor (represented by two parallel short lines, spacing about 0.8 cm, length 1.5 cm), labeled " $C$ " (#1E293B)
    - A Josephson junction, represented by a cross symbol, labeled " $E_J$ " (#DC2626)
    - Capacitor and Josephson junction connected in parallel
  - Draw a simplified microwave transmission line above the circuit (a horizontal line with a small arrow indicating microwave input), labeled “Microwave Drive Line,” color #F59E0B
  - Draw a simplified readout resonator to the right of the circuit (another LC circuit, smaller), connected to the main circuit by a coupling line, labeled “Readout Resonator,” color #10B981
  - Enclose the entire circuit in a dashed box, labeled “Transmon Qubit”
  - Add a note next to the Josephson junction: “anharmonicity ~ 200-300 MHz”
3. Right Side — Energy Level Diagram:
  - Draw a series of horizontal lines representing energy levels, labeled from top to bottom:
    - $|2\rangle$ : Second excited state, color #92400E, line length 3 cm
    - $|1\rangle$ : First excited state, color #F59E0B, line length 3 cm
    - $|0\rangle$ : Ground state, color #0D9488, line length 3 cm
  - Energy level spacing: The gap from $|0\rangle$ to $|1\rangle$ is larger, labeled ” $\omega_{01} \approx 4-8$ GHz”; the gap from $|1\rangle$ to $|2\rangle$ is slightly smaller, labeled " $\omega_{12} = \omega_{01} - \alpha$ " ( $\alpha$ is the anharmonicity)
  - Draw an upward wavy arrow from $|0\rangle$ to $|1\rangle$ (representing microwave photon absorption), color #F59E0B, labeled " $\hbar\omega$ "
  - Add a warning icon and text next to the $|2\rangle$ level: “Avoid leakage to $|2\rangle$ — use DRAG pulse shaping”
4. Bottom Note: Spanning both columns: “The Transmon suppresses charge noise through the $E_J \gg E_C$ design, while retaining sufficient anharmonicity for selective single-qubit transitions.”
Size Suggestion: Width 18 cm x Height 10 cm
Font: Title 11 pt, labels 9 pt, formulas 9 pt

ASCII Placeholder:

  [Circuit]                    [Energy Levels]
   ────||────                  |2⟩  ──── (~leakage)
       │                       |1⟩  ──── ω₁₂ = ω₀₁ - α
      [×] EJ                   |0⟩  ────
       │                          ↑ microwave ω₀₁ ≈ 4-8 GHz
   [Readout Cavity]                  [Anharmonicity ensures selective transitions]
  
  [Transmon: E_J >> E_C → Charge noise insensitive]

Diagram 14: Shor’s Algorithm — Quantum Phase Estimation (QPE) Core Structure

Shor’s Algorithm — Quantum Phase Estimation (QPE) Core Structure

Chapter: Chapter 3 “Shor’s Algorithm” / Section 3.1
Purpose: Show the high-level circuit structure of the QPE subroutine in Shor’s algorithm, highlighting its modular design.
Recommended Tools: Qiskit, TikZ (quantikz)、draw.io
Detailed Description:
1. Layout: Use a “black box” abstraction level, showing the input-processing-output flow of QPE.
2. Input Region (left):
  - Top: $t$ horizontal lines (counting register), labeled " $|0\rangle^{\otimes t}$ " (#0D9488), with $t$ satisfying $t = 2L + 1 + \lceil\log(2 + \frac{1}{2\epsilon})\rceil$ (small-font note)
  - Bottom: one horizontal line (target register), labeled ” $|\psi\rangle$ (eigenstate of $U$ )” (#7C3AED)
3. Processing Region (large central box):
  - Draw a large rectangular box, border #2563EB (line width 2 pt), fill #EFF6FF (20% opacity)
  - Divide the box into upper and lower parts:
    - Upper part (Hadamard layer): All counting register lines pass through $H$ gates, preparing a uniform superposition state
    - Lower part (Controlled- $U^{2^k}$ layer):
      - Draw controlled gates from each counting register line downward to the target register
      - The $k$ th line (from top) controls the $U^{2^k}$ operation
      - Control: solid dot (#2563EB)
      - Target: box labeled " $U^{2^k}$ " (#DC2626)
      - Controlled gates arranged from left to right: $U^{2^0}, U^{2^1}, U^{2^2}, \ldots, U^{2^{t-1}}$
  - Label above the box: “Quantum Phase Estimation”
4. QFT Region (right):
  - Draw a sub-box to the right of the counting register, labeled “Inverse QFT $^{\dagger}$ ”
  - Inside the box, show a simplified QFT circuit (referencing Diagram 12 style, but compressed)
5. Output Region (far right):
  - Counting register output: " $|\tilde{\theta}\rangle$ " (#10B981), labeled “ $t$ -bit binary approximation of $\theta$ ”
  - Target register output: " $|\psi\rangle$ " (unchanged)
6. Formula Notes (below diagram):
  - " $U|\psi\rangle = e^{2\pi i \theta}|\psi\rangle \xrightarrow{\text{QPE}} |\tilde{\theta}\rangle|\psi\rangle$ "
  - “Precision: $|\theta - \tilde{\theta}| \le 2^{-t}$ , success probability $\ge 1 - \epsilon$ ”
  - “Application in Shor’s algorithm: $U|y\rangle = |ay \bmod N\rangle$ , estimate $\theta$ -> extract order $r$ -> factor”
7. Key Path Highlight: Use a thick #F59E0B arrow pointing from input to output, labeled “Quantum Core of Shor’s Algorithm”
Size Suggestion: Width 20 cm x Height 12 cm
Font: Register labels 10 pt, box labels 9 pt, formulas 9 pt

ASCII Placeholder:

  |0⟩^⊗t ───[H^⊗t]───┬───┬───┬───┐───[QFT†]─── |θ̃⟩ (t-bit)
                     │   │   │   │
                     U¹  U²  U⁴  U^{2^{t-1}}
                     │   │   │   │
  |ψ⟩    ────────────●───●───●───●─────────── |ψ⟩
  
  [QPE: U|ψ⟩=e^{2πiθ}|ψ⟩ → estimate θ → Shor core]

Diagram 15: Grover’s Algorithm — Amplitude Amplification Geometry

Grover’s Algorithm — Amplitude Amplification Geometry

Chapter: Chapter 3 “Grover’s Algorithm” / Section 3.2
Purpose: Use geometric figures to show the amplitude amplification mechanism of Grover’s algorithm — a rotation in a 2D subspace.
Recommended Tools: TikZ (LaTeX), Matplotlib (Python)、Adobe Illustrator
Detailed Description:
1. Coordinate System: A 2D planar coordinate system, without labeled axes, using only two orthogonal basis vectors to define the space.
2. Basis Vectors:
  - Draw two orthogonal normalized basis vectors:
    - " $|s\rangle$ ": Uniform superposition state (equal-weight superposition of all solutions), direction toward upper right at about 30 degrees, color #2563EB, line width 2 pt
    - " $|s'\rangle$ ": Orthogonal to $|s\rangle$ , direction toward upper left at about 60 degrees, color #4B5563, line width 1.5 pt (dashed)
  - Label next to $|s\rangle$ : " $|s\rangle = \frac{1}{\sqrt{N}}\sum_x |x\rangle$ "
3. Target State:
  - Draw " $|\omega\rangle$ " (target solution), located near the $|s'\rangle$ direction, color #10B981, line width 2 pt
  - Label ” $|\omega\rangle$ : target solution”
4. Rotation Process (multiple iterations):
  - Initial state: $|s\rangle$ (#2563EB)
  - Iteration 1: Draw a vector moving from $|s\rangle$ toward $|\omega\rangle$ , color #7C3AED, line width 1.5 pt, labeled “Oracle + Diffusion”
  - Iteration 2: A vector continuing to move toward $|\omega\rangle$ , color #DC2626, line width 1.5 pt
  - Iteration $k$ : A vector finally approaching $|\omega\rangle$ , color #10B981, line width 2.5 pt, labeled " $k \approx \frac{\pi}{4}\sqrt{N}$ "
  - Mark the end of each vector with a small dot, dot color matching the vector, diameter 5 pt
  - Use an arc (color #F59E0B) to label the rotation angle " $2\theta$ " per iteration, where $\sin\theta = \frac{1}{\sqrt{N}}$
5. Reflection Operation Notes:
  - Add two small schematics on the right side:
    - “Oracle reflection”: reflection about the " $|s'\rangle$ " axis, reversing the amplitude of the target solution
    - “Diffusion reflection”: reflection about the $|s\rangle$ axis, flipping all amplitudes about the average
  - Each small schematic uses a simplified vector diagram showing the state before and after reflection
6. Performance Comparison:
  - Add a comparison box at the bottom of the diagram:
    - Classical search: $O(N)$ queries
    - Grover quantum search: $O(\sqrt{N})$ queries
    - Highlight the quantum speedup factor in #10B981: $\sqrt{N}$ times
7. Formula: Add at the top left of the diagram: ” $G = (2|s\rangle\langle s| - I)O$ , where $O = I - 2|\omega\rangle\langle\omega|$ ”
Size Suggestion: Width 16 cm x Height 14 cm
Font: Basis vector labels 11 pt, iteration labels 10 pt, formulas 9 pt

ASCII Placeholder:

          |s'⟩
           │
     ──────┼──────
           │  ↗ kth iteration ≈ π/4·√N
           │ ↗
    |s⟩ ───●──→ |ω⟩ (Target)
           ↖
            ↖ 1st iteration
  
  [Grover: Each iteration rotates by 2θ, sinθ=1/√N]
  [Classical O(N) → Quantum O(√N)]

Diagram 16: Decoherence — $T_1$ Relaxation and $T_2$ Dephasing

Decoherence — $T_1$ Relaxation and $T_2$ Dephasing

Chapter: Chapter 5 “Decoherence and Noise Sources” / Section 5.2
Purpose: Use exponential decay curves to contrast $T_1$ and $T_2$ decoherence mechanisms, showing how quantum information is lost over time.
Recommended Tools: Matplotlib (Python), TikZ (pgfplots), OriginLab
Detailed Description:
1. Layout: Two subplots, one above the other, sharing the horizontal axis (time $t$ ).
2. Upper Subplot — $T_1$ Relaxation (Energy Relaxation):
  - Title: ” $T_1$ Relaxation / Energy Relaxation”
  - Horizontal axis: time $t$ ( $\mu$ s), range 0—500 $\mu$ s
  - Vertical axis: excited state population $P_1(t)$ , range 0—1
  - Draw an exponential decay curve: $P_1(t) = e^{-t/T_1}$ , with $T_1 = 100$ $\mu$ s
  - Curve color #F59E0B (Energy Orange), line width 2 pt
  - Draw a vertical dashed line at $t = T_1$ (#4B5563, dash), labeled ” $T_1 = 100$ $\mu$ s”
  - Label at $t = T_1$ : " $P_1(T_1) = 1/e \approx 0.368$ "
  - Label at $t = 0$ : " $P_1(0) = 1$ "
  - Add a simplified energy level transition schematic on the right: an arrow from $|1\rangle$ to $|0\rangle$ , labeled “Energy dissipated to environment”
  - Fill area: fill below the curve with #FEF3C7 (light orange, 30% opacity)
3. Lower Subplot — $T_2$ Dephasing:
  - Title: ” $T_2$ Dephasing”
  - Horizontal axis: time $t$ ( $\mu$ s), range 0—500 $\mu$ s
  - Vertical axis: coherence term $|\rho_{01}(t)|$ , range 0—1
  - Draw an exponential decay curve: $|\rho_{01}(t)| = e^{-t/T_2}$ , with $T_2 = 100$ $\mu$ s
  - Curve color #7C3AED (Superposition Purple), line width 2 pt
  - Draw a vertical dashed line at $t = T_2$ , labeled ” $T_2 = 100$ $\mu$ s”
  - Label at $t = 0$ : " $|\rho_{01}(0)| = 0.5$ " (for a pure state)
  - Add a simplified Bloch sphere cross-section on the right: show the Bloch vector gradually contracting from the equator (pure superposition) to the $z$ axis (mixed state), represented by a series of progressively shorter vectors
  - Fill area: fill below the curve with #F3E8FF (light purple, 30% opacity)
4. Overall Labels:
  - Add a relationship between the two subplots: “Typically $T_2 \le 2T_1$ . If $T_2 = T_1$ , decoherence is entirely dominated by energy relaxation; if $T_2 \ll T_1$ , there is an additional pure dephasing mechanism.”
  - Add a small comparison table of typical values for different platforms at the very bottom:
    Platform $T_1$ $T_2$
    Superconducting 100 $\mu$ s 100 $\mu$ s
    Ion Trap >1 min 1-100 s
    Silicon Spin 10 s 2 ms
5. Emphasis: Add a warning at the bottom in #DC2626: “Note: $T_2$ is one of the most critical limiting factors in quantum computing. If the quantum circuit execution time $\gg T_2$ , the result will be completely overwhelmed by noise.”
Size Suggestion: Width 16 cm x Height 14 cm
Font: Subplot titles 11 pt, axis labels 10 pt, notes 9 pt

Platform	$T_1$	$T_2$
Superconducting	100 $\mu$ s	100 $\mu$ s
Ion Trap	>1 min	1-100 s
Silicon Spin	10 s	2 ms

ASCII Placeholder:

  P₁(t) │1.0                    ρ₀₁(t) │0.5
        │*                        │*
        │ *                       │ *
        │  *  T₁=100μs            │  *  T₂=100μs
        │   *                     │   *
        └────├────────→ t         └────├────────→ t
        0   100  500 μs           0   100  500 μs
  [T₁: Energy leaks from |1⟩ to |0⟩]    [T₂: Phase random drift]

Diagram 17: Surface Code — 2D Lattice and Stabilizer Measurements

Surface Code — 2D Lattice and Stabilizer Measurements

Chapter: Chapter 5 “Quantum Error Correction” / Section 5.3
Purpose: Show the 2D lattice structure of the surface code, $X$ -type and $Z$ -type plaquette stabilizer measurements, and the encoding of logical qubits.
Recommended Tools: TikZ (LaTeX), Adobe Illustrator、Python (Matplotlib)
Detailed Description:
1. Layout: Main figure is the lattice structure, with legend and notes at the bottom right.
2. Lattice Structure:
  - Draw a 5x5 square grid (25 vertices total), with a dot at each vertex representing a physical qubit
  - Dot diameter 0.4 cm, line width 1 pt
  - Data qubits: Located at the “vertex” positions of the grid, filled with Quantum Blue (#2563EB)
  - Measurement qubits (measure qubits):
    - $X$ -type stabilizer measurement qubits: Located at the “face center” positions (black squares), filled with Entanglement Red (#DC2626), with a small " $X$ " label inside
    - $Z$ -type stabilizer measurement qubits: Located at the “face center” positions (white squares), filled with Ground Teal (#0D9488), with a small " $Z$ " label inside
  - Use a checkerboard pattern to distinguish $X$ -type and $Z$ -type stabilizer faces
3. Stabilizer Illustration:
  - Select an $X$ -type plaquette (e.g., a black square in the center), frame it with a thick red line (#DC2626, line width 2 pt), and draw connecting lines from the center to the four corner data qubits, labeled " $X_1 X_2 X_3 X_4$ "
  - Select an adjacent $Z$ -type plaquette (white square), frame it with a thick teal line (#0D9488, line width 2 pt), labeled " $Z_1 Z_2 Z_3 Z_4$ "
  - Add a small note beside the frame: “Periodic measurement of these stabilizer syndromes can locate nearest-neighbor $X$ errors and $Z$ errors”
4. Logical Operators:
  - Use a thick green chain line (#10B981, line width 3 pt) spanning the entire lattice from left edge to right edge, connecting a series of data qubits, labeled “Logical $\bar{Z}$ operator”
  - Use a thick orange chain line (#F59E0B, line width 3 pt) spanning the lattice from top edge to bottom edge, labeled “Logical $\bar{X}$ operator”
  - Note: The logical qubit information is encoded in these non-local chain operators, so local errors do not destroy the logical information
5. Code Distance Note:
  - Label outside the lattice: “Code Distance $d = 3$ ” (for this 5x5 example)
  - Add formula: “Can correct up to $(d-1)/2 = 1$ arbitrary physical error”
6. Legend (bottom right):
  - Blue dot: Data Qubit
  - Red dot: $X$ -type Ancilla
  - Teal dot: $Z$ -type Ancilla
  - Green line: Logical $Z$ chain
  - Orange line: Logical $X$ chain
7. Key Parameters Box (bottom left):
  - Threshold: $p_{\text{th}} \approx 1\%$
  - Physical-to-logical qubit ratio: ~1500:1 (surface code, 0.1% error rate)
  - 2024 breakthrough: Google Willow, distance-7 surface code, logical lifetime > physical lifetime
Size Suggestion: Width 16 cm x Height 14 cm
Font: Qubit labels 7 pt, box labels 9 pt, notes 8 pt

ASCII Placeholder:

    ●─●─●─●─●
    │ │ │ │ │
    ●─●─●─●─●
    │ │X│Z│ │
    ●─●─●─●─●
    │ │ │ │ │
    ●─●─●─●─●
    
  ●=Data qubit  X=X measurement  Z=Z measurement
  [Green]=Logical Z  [Orange]=Logical X
  
  [Surface Code: d=3, correct (d-1)/2 errors]

Diagram 18: Quantum Computing Development Timeline

Quantum Computing Development Timeline

Chapter: Chapter 4 “Key Milestones” / Section 4, and Chapter 5 “Timeline Outlook” / Section 5.5
Purpose: Show key milestones in quantum computing from theory to experiment in a timeline format, along with future outlook.
Recommended Tools: TikZ (LaTeX), Adobe Illustrator、draw.io
Detailed Description:
1. Layout: Horizontal timeline extending from 1980 to 2040, divided into three regions — “Past,” “Present,” and “Future” — distinguished by different background colors.
2. Timeline:
  - A thick horizontal line (#1E293B, line width 2 pt) running through the entire diagram
  - Year tick marks below: 1980, 1990, 2000, 2010, 2015, 2019, 2021, 2023, 2024, 2030, 2035, 2040
  - Tick color #4B5563
3. Milestone Events (label boxes extending above or below the timeline):
  - 1981 (up): Richard Feynman proposes “quantum simulation” concept, box color #4B5563
  - 1985 (down): David Deutsch proposes “universal quantum computer” concept, box color #4B5563
  - 1994 (up): Peter Shor proposes Shor’s algorithm, box color #2563EB
  - 1996 (down): Lov Grover proposes Grover’s algorithm, box color #7C3AED
  - 1998 (up): First quantum error-correcting code experiment, box color #4B5563
  - 2019 (up, highlight): Google Sycamore claims quantum supremacy, box color #F59E0B, border bold (2 pt)
  - 2021 (down, highlight): China’s “Jiuzhang” photonic quantum advantage, box color #F59E0B, border bold
  - 2023 (up, highlight): IBM Eagle quantum utility, box color #F59E0B
  - 2024 (down, highlight): Google Willow sub-threshold error correction, box color #10B981, border bold, labeled “Major Breakthrough”
  - 2026-2030 (up, dashed box): “Quantum Utility” expected, box color #2563EB, border dashed
  - 2030-2035 (down, dashed box): “Fault-Tolerant Qubits” expected, box color #10B981, border dashed
  - 2035+ (up, dashed box): “Broad Quantum Advantage” expected, box color #7C3AED, border dashed
4. Region Background Colors:
  - “Past” (1980—2018): background #F8FAFC
  - “Present” (2019—2025): background #EFF6FF (light blue), labeled “NISQ Era”
  - “Future” (2026—2040): background #F0FDF4 (light green), border dashed
5. Supplementary Information:
  - Add a qubit count growth curve (inset) at the bottom, showing the exponential growth trend from 2 qubits in 1998 to 1000+ qubits in 2024
  - Curve color #2563EB, label qubit counts at key milestones
6. Overall Title: “Milestones in Quantum Computing,” font 14 pt, bold, centered.
Size Suggestion: Width 20 cm x Height 12 cm
Font: Event boxes 8 pt, year ticks 9 pt, region titles 11 pt

ASCII Placeholder:

  1980───1994───2019───2024───2030───2040──→
   │      │      │      │       │       │
  Feynman Shor  Google  Willow  Utility    Fault-tolerant
  Proposed algorithm   Sycamore ⭐Breakthrough   Advantage   Quantum
  
  [Past]        [NISQ Present]      [Future]

Appendix A: ASCII Placeholder Summary Table

Diagram #	Title	Recommended Tutorial Location
Fig 1	Complex plane — Addition	Section 1.1 Quantum Superposition Math
Fig 2	Complex plane — Multiplication	Section 1.1 Quantum Superposition Math
Fig 3	Classical bit vs qubit	Section 2.1 Information Unit and State Space
Fig 4	Bloch sphere overview	Section 1.1 Bloch Sphere Representation
Fig 5	Bloch sphere gate operations	Section 3.1 Universal Quantum Gate Set
Fig 6	Double-slit experiment	Section 1.3 Quantum Interference
Fig 7	Measurement and wavefunction collapse	Section 2.3 Measurement
Fig 8	Bell state circuit	Section 2.1 Entanglement / Section 3.1
Fig 9	Quantum teleportation	Quantum communication topic (extension)
Fig 10	GHZ state circuit	Multi-partite entanglement extension
Fig 11	Bell state correlation table	Section 1.2 Quantum Entanglement
Fig 12	QFT circuit (n=3)	Section 3.3 QFT
Fig 13	Transmon schematic	Section 1.2 Superconducting Qubit
Fig 14	Shor QPE structure	Section 3.1 Shor Algorithm
Fig 15	Grover amplitude amplification	Section 3.2 Grover Algorithm
Fig 16	T1/T2 decoherence	Section 5.2 Decoherence
Fig 17	Surface code lattice	Section 5.3 Quantum Error Correction
Fig 18	Development timeline	Section 4 Milestones / Section 5.5 Outlook

Appendix B: Tool Selection Recommendations

Tool	Applicable Diagrams	Advantages	Disadvantages
TikZ (LaTeX)	All diagrams	Vector output, perfect LaTeX integration, precise control	Steep learning curve, verbose code
Qiskit (Python)	Figs 8-10, 12, 14	Automatic standard quantum circuits, built-in styles	Limited customization, Python-dependent
Matplotlib (Python)	Figs 1-2, 15-16	Scientific plotting standard, rich Python ecosystem	Default styles need heavy tuning
Adobe Illustrator	Figs 3, 6-7, 13, 17-18	Full visual editing, best artistic results	Proprietary, time-consuming manual drawing
Inkscape	Figs 3, 6-7, 13, 17-18	Open source, strong vector editing	Moderate learning curve
Blender	Figs 4-5	Extremely high 3D rendering quality	Overly complex, vector export difficult
QuTiP (Python)	Figs 4-5, 15	Quantum-specific visualization, built-in Bloch sphere	Fixed styling, customization requires hacking

Appendix C: File Naming and Versioning Conventions

It is recommended to create independent vector files for each diagram, with the following naming convention:

fig{N}_{short_name}.{ext}

Examples:
fig01_complex_addition.pdf
fig02_complex_multiplication.pdf
fig03_classical_vs_qubit.pdf
fig04_bloch_sphere_overview.pdf
fig05_bloch_gates.pdf
fig06_double_slit.pdf
fig07_measurement_collapse.pdf
fig08_bell_state_circuit.pdf
fig09_teleportation_circuit.pdf
fig10_ghz_circuit.pdf
fig11_bell_correlation.pdf
fig12_qft_circuit.pdf
fig13_transmon_schematic.pdf
fig14_shor_qpe.pdf
fig15_grover_amplitude.pdf
fig16_t1_t2_decoherence.pdf
fig17_surface_code.pdf
fig18_timeline.pdf

Recommended format priority: PDF (vector) > SVG (vector) > PNG (high resolution 300 DPI) > JPEG (not recommended)

Document version: v1.0 Creation date: 2026-05-28 Applicable tutorial: Quantum Computing Primer Language: English

Chapter 6: Engineering Outlook

Chapter 6: Outlook — From Current State to Early Prototypes

6.1 Current State of the Art

Superconducting Route: Willow’s Breakthrough and Limitations

Ion Trap Route: Quantinuum H2’s Logical Gate Demonstration

Early Progress on Other Platforms

The Common Gap: Not a Computer

6.2 Qubit Scale-Up: From 10210^2102 to 103–410^{3\text{--}4}103–4

Superconducting Route: The Triple Dilemma of Fabrication, Wiring, and Crosstalk

Ion Trap Route: Single-Trap Limits and Modular Interconnection

Neutral Atom Route: Quantity Lead, Fidelity Catch-Up

Silicon Spin Route: CMOS Compatibility vs. Uniformity

Quantified Metrics: How Many Physical Qubits for an Early Prototype?

6.3 Universal Fault-Tolerant Gates: From Clifford to Clifford+T

The Current Logic Gate Gap

Why Logical TTT Gates Are Harder Than Clifford Gates

Error Rate Target for Logical TTT Gates

Logical TTT Gate Paths by Platform

6.4 Magic State Distillation at Scale

Quantitative Analysis of Distillation Overhead

Chip Architecture for Magic State Factories

Key Metric: Magic States/Second

6.5 Real-Time Decoders: From FPGA to ASIC

Computational Complexity of the Decoding Problem

The Race Between Latency and Coherence Time

The Inevitability of Moving from FPGA to ASIC

Distributed Decoding Architecture

6.6 Cryogenic and Control System Integration

Current Demonstration vs. Early Prototype: System-Level Comparison

Core Contradiction: The 3-Orders-of-Magnitude Gap Between Heat Load and Cooling Power

Custom ASIC Requirements for Control Electronics

Auto-Calibration: From Hundreds to Thousands of Parameters

6.7 Logical Qubit Interconnect and Efficient Codes

Physical Qubit Overhead of the Surface Code

Quantum LDPC Codes: Theoretical Hope for Reducing Overhead

Logical Qubit Interconnection: Bus Transport and Error Correction

6.8 Timeline and Roadmap: Not a Prophecy, But an Engineering Checklist

Key Milestones and Timeline

Milestone 1: 100 Logical Qubits + Full Clifford Gates (2027—2028)

Milestone 2: Logical TTT Gate Error <10−6<10^{-6}<10−6 (2028—2029)

Milestone 3: Early Prototype (2030—2033)

Milestone 4: Practical Quantum Computing (2035+)

Sources of Uncertainty

Closing: The Beginning of an Engineering Roadmap

Chapter 6 Summary

Appendix

Quantum Computing Tutorial Visual Diagram Specifications

Quantum Computing Tutorial — Visual Diagram Specifications

Overview

Global Color Palette

Diagram Specifications

Diagram 1: Complex Plane — Addition (Parallelogram Rule)

Diagram 2: Complex Plane — Multiplication (Rotation + Scaling)

Diagram 3: Classical Bit vs Qubit — State Space Comparison

Diagram 4: Bloch Sphere — 3D Wireframe Overview

Diagram 5: Bloch Sphere — Single-Qubit Gate Operations

Diagram 6: Double-Slit Experiment — Schematic Diagram

Diagram 7: Quantum Measurement and Wavefunction Collapse

Diagram 8: Quantum Circuit — Bell State Preparation

Diagram 9: Quantum Circuit — Quantum Teleportation

Diagram 10: Quantum Circuit — GHZ State Preparation

Diagram 11: Entanglement Correlation — Bell State Measurement Table

Diagram 12: Quantum Fourier Transform (QFT) Circuit — n=3 Case

Diagram 13: Superconducting Qubit — Transmon Simplified Schematic

Diagram 14: Shor’s Algorithm — Quantum Phase Estimation (QPE) Core Structure

Diagram 15: Grover’s Algorithm — Amplitude Amplification Geometry

Diagram 16: Decoherence — T1T_1T1​ Relaxation and T2T_2T2​ Dephasing

Diagram 17: Surface Code — 2D Lattice and Stabilizer Measurements

Diagram 18: Quantum Computing Development Timeline

Appendix A: ASCII Placeholder Summary Table

Appendix B: Tool Selection Recommendations

Appendix C: File Naming and Versioning Conventions

6.2 Qubit Scale-Up: From $10^2$ to $10^{3\text{--}4}$

Why Logical $T$ Gates Are Harder Than Clifford Gates

Error Rate Target for Logical $T$ Gates

Logical $T$ Gate Paths by Platform

Milestone 2: Logical $T$ Gate Error $<10^{-6}$ (2028—2029)

Diagram 16: Decoherence — $T_1$ Relaxation and $T_2$ Dephasing